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PDF ADM1487 Data sheet ( Hoja de datos )
| Número de pieza | ADM1487 | |
| Descripción | Ultralow Power RS-485/RS-422 Transceiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADM1487 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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PRELIMINARY TECHNICAL DATA
a
Ultra-Low Power RS-485/RS-422 Transceiver
with Low EMI and +/-10kV ESD Protection
Preliminary Technical Data
ADM1487
FEATURES
Low Power - 120µA Max ICC with Driver Disabled
High Input Impedance — Up to 256 Transceivers on Bus
Low-Current (1µA) Shutdown Mode
Slew Rate Control for Error-Free Data
Transmission and Low EMI
±10kV ESD Protection (Human Body Model) on
RS-485 I/O pins
Thermal Protection of Driver
Glitch-Free Driver Power-Up Allows Hot Connection
Driver Maintains High Output Impedance with Power
Off
Wide Common-Mode Range Allows ±7V Ground Differ-
ences Between Devices
Pin-Compatible with Industry Standard 75176
APPLICATIONS
Battery-Powered RS-485/RS-422 Systems
Level Translation
GENERAL DESCRIPTION
The ADM1487 is an ultra-low power RS-485/RS-422
transceiver consisting of one driver and one receiver per
package. Quiescent operating current is typically 80µA
and 1µA in shutdown mode. The driver and receiver both
have three-state outputs. This allows multiple drivers to be
connected to an RS-485/RS-422 bus, or several receiver
outputs to be connected to a serial data bus. The driver
will maintain a high-impedance output state even with
power off, while the receiver features fail-safe operation
that guarantees a logic high output if the inputs are left
open-circuit.
The device has slew-rate limited drivers to minimize elec-
tromagnetic interference (EMI) and reduce reflections
caused by incorrectly terminated cables.
FUNCTIONAL BLOCK DIAGRAM
RO 1
w RE 2
w DE 3
w DI 4
R
D
8 VCC
7B
6A
5 GND
.D ADM1487
ataSheetREV. PrC 08/02
4Information furnished by Analog Devices is believed to be accurate and
Ureliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
.which may result from its use. No license is granted by implication or
comotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
–1–
1 page  
PRELIMINARY TECHNICAL DATA
ADM1487 TEST CIRCUITS AND TIMING
ADM1487
A
VOD
A
R
R
VOC
Figure 1. Driver DC Load Test Circuit
OUTPUT
UNDER
TEST
VCC
TEST
POINT
500V
CRL
15pF
S1
S2
3V
DE
DI
D
A
VOD2
B
RDIFF
CL1
CL2
A
R
B
15pF
RO
Figure 2. Driver/Receiver Timing Test Circuit
3V
DI
0V
B
A
V0
VDIFF 0V
-V0
1.5V
f = 1MHz, tr # 10ns, tf # 10ns
tDPLH
tDPHL
V0
V0/2
10%
90%
VDIFF = VA - VB
90%
tDR tDF
tSKEW = |tDPLH-tDPHL|
10%
Figure 3. Driver Propagation Delays
A VOD2
B -VOD2
VOH
RO
VOL
f = 1MHz, tr # 10ns, tf # 10ns
tRPHL
tRPLH
Figure 4. Receiver Propagation Delays
1.5V
Figure 5. Test Load for Driver Enable/Disable Time Test
3V
DE
0V
5V
A, B
VOL
VOH
A, B
VOL
f = 1MHz, tr # 10ns, tf # 10ns
1.5V
tDZL(SHDN), tDZL
tDLZ
2.3V
OUTPUT NORMALLY LOW
VOL+ 0.5V
OUTPUT NORMALLY HIGH
2.3
VOH- 0.5V
VtDZH(SHDN), tDZH
tDHZ
Figure 6. Driver Enable and Disable Times
VCC
TEST
POINT
RO
CRL
15pF
1kV
S1
S2
1kV
Figure 7. Test Load for Receiver Enable/Disable Time Test
3V
RE
0V
5V
RO
f = 1MHz, tr # 10ns, tf # 10ns
tRZL(SHDN), tRZL
1.5 OUTPUT NORMALLY LOW
V
tRLZ
1.5
V
0.5V
5V
RO
0V
OUTPUT NORMALLY HIGH
1.5
VtRZH(SHDN), tRZH
tRHZ
0.5V
Figure 8. Receiver Enable and Disable Delay Times
Rev. PrC
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ADM1487.PDF ] | |
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