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Número de pieza | UT69RH051 | |
Descripción | Radiation-Hardened MicroController | |
Fabricantes | Aeroflex Circuit Technology | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de UT69RH051 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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UT69RH051 Radiation-Hardened MicroController
Data Sheet
June 2004
FEATURES
Three 16-bit timer/counters
- High speed output
- Compare/capture
- Pulse width modulator
- Watchdog timer capabilities
256 bytes of on-chip data RAM
32 programmable I/O lines
7 interrupt sources
Programmable serial channel with:
- Framing error detection
- Automatic address recognition
TTL and CMOS compatible logic levels
64K external data and program memory space
MCS-51 fully compatible instruction set
Flexible clock operation
- 1Hz to 20MHz with external clock
- 2MHz to 20MHz using internal oscillator with external
crystal
Radiation-hardened process and design; total dose irradia-
tion testing MIL-STD-883 Method 1019
- Total dose: 1.0E6 rads(Si)
- Latchup immune
Packaging options:
- 40-pin 100-mil center DIP (0.600 x 2.00)
- 44-lead 25-mil center Flatpack (0.670 x 0.800)
Standard Microcircuit Drawing 5962-95638 available
- QML Q & V compliant
PORT 0
DRIVERS
PORT 2
DRIVERS
PSEN
ALE
EA
RST
RAM
PORT 0
LATCH
PORT 2
LATCH
B
REGISTER
ACC
TMP2
TMP1
ALU
PSW TMP3
STACK
POINTER
SPECIAL FUNCTION
REGISTERS,
TIMERS,
PCA,
SERIAL PORT
PORT 1
LATCH
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
PORT 3
LATCH
OSC.
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0 - P1.7
P3.0 - P3.7
Figure 1. UT69RH051 MicroController Block Diagram
-1
1 page F8
INDIRECT
ACCESS
ONLY
F0
•
•
•
88
80
78
70
•
•
•
38
DIRECT OR 30
INDIRECT
ACCESS 28
20
18
10
08
00
8 BYTES
FF
F7
•
•
•
8F SCRATCH
87 PAD AREA
7F
77
•
•
•
3F
37
2F BIT
ADDRESSABLE
27 SEGMENT
1F
17 REGISTER
BANKS
0F
07
Figure 3. Internal Data Memory Organization
2.1.3 Reset
The reset input is the RST pin. To reset, hold the RST pin high
for a minimum of 24 oscillator periods while the oscillator is
running. The CPU generates an internal reset from the external
signal. The port pins are driven to the reset state as soon as a valid
high is detected on the RST pin.
While RST is high, PSEN and the port pins are pulled high; ALE
is pulled low. All SFRs are reset to their reset values as shown
in table 3. The internal Data Memory content is indeterminate.
The processor will begin operation one machine cycle after the
RST line is brought low. A memory access occurs immediately
after the RST line is brought low, but the data is not brought into
the processor. The memory access repeats on the next machine
cycle and actual processing begins at that time.
5
5 Page ALE
PSEN
PORT 0
PORT 2
tLHLL
tLLPL
tAVLL
tLLAX
A0 - A7
tPLPH
tLLIV
tPLIV
tPLAZ
tPXIX
INSTR IN
tAVIV
A8 - A15
tPXIZ
A0 - A7
A8 - A15
Figure 6. External Program Memory Read Timing Waveforms
ALE
PSEN
RD
PORT 0
PORT 2
tLHLL
tLLDV
tLLWL
tAVLL
tRLDV
tLLAX
A0 -A7 FROM RI OR DPL
tRLRH
tRLAZ
tRHDX
DATA IN
tWHLH
tRHDZ
A0 - A7 FROM PCL
INSTR IN
tAVWL
tAVDV
P2.0 - P2.7 OR A8 -A15 FROM DPH
A8 - A15 FROM PCH
Figure 7. External Data Memory Read Cycle Waveforms
ALE
PSEN
WR
PORT 0
PORT 2
tLHLL
tWHLH
tAVLL
tLLWL
tLLAX
tQVWX
A0 -A7 FROM RI OR DPL
tWLWH
tQVWH
DATA OUT
tWHQX
A0 - A7 FROM PCL
INSTR IN
tAVWL
P2.0 - P2.7 OR A8 -A15 FROM DPH
A8 - A15 FROM PCH
Figure 8. External Data Memory Write Cycle Waveforms
11
11 Page |
Páginas | Total 19 Páginas | |
PDF Descargar | [ Datasheet UT69RH051.PDF ] |
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