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PDF SII141 Data sheet ( Hoja de datos )
| Número de pieza | SII141 | |
| Descripción | Panellink(r) Digital Receiver | |
| Fabricantes | Silicon Image | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SII141 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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SiI 141
PanelLink® Digital Receiver
July 1999
General Description
The SiI 141 uses PanelLink Digital technology to support displays ranging
from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD desktop
monitor applications. With a flexible single or dual pixel out interface and
selectable output drive, the SiI 141 receiver supports up to true color panels (24
bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2 pixel/clock mode).
PanelLink also features an inter-pair skew tolerance up to 1 full input clock cycle
and a highly jitter tolerant PLL design. Since all PanelLink products are
designed on scaleable CMOS architecture to support future performance
requirements while maintaining the same logical interface, system designers can
be assured that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of the
system level issues associated with high-speed digital design, providing the
system designer with a digital interface solution that is quicker to market and
lower in cost.
Features
• Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh
XGA)
• Low Power: 3.3V core operation & power-down mode
• High Skew Tolerance: 1 full input clock cycle (15ns at 65
MHz)
• Pin-compatible with SiI101
• Sync Detect: for Plug & Display “Hot Plugging”
• Cable Distance Support: over 5m with twisted-pair, fiber-
optics ready
• Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&DTM and DFP)
SiI141 Pin Diagram
24-bit Input Data for 1-pixel/clock mode
8-bit Channel 2 Data
1-pixel/clock
8-bit Channel 1 Data
1-pixel/clock
8-bit Channel 0 Data
1-pixel/clock
18-bit Even Data for 2-pixel/clock mode
6-bit Odd Channel 0
Data 2-pixel/clock
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
DE
Q20
Q21
Q22
Q23
OGND
Q24
OVCC
Q25
VCC
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SiI141
80-Pin TQFP
(Top View)
20 Q4
19 Q3
18 Q2
17 Q1
16 Q0
15 OVCC
14 VSYNC
13 OGND
12 HSYNC
11 GND
10 CTL3
9 CTL2
8 CTL1
7 SCDT
6 DFO
5 PIXS
4 OGND
3 PDO
2 PD
1 RESERVED
Functional Block Diagram
ST
PIXS
DFO
OCK_INV
PDO
EXT_RES
RX2+
RX2-
RX1+
RX1-
Termination
Control
VCR
DATA
RECOVERY
CH2
VCR
DATA
RECOVERY
CH1
INTER-
CHANNEL
SYNC.
8
CLT3
CLT2
DE2
24/36
Q[35:0/23:0]
ODCK
DE
8
CLT1
PANEL
INTER-
FACE
DECODER PLL_SYNC LOGIC
HSYNC
VSYNC
DE1
SCDT
RX0+
RX0-
VCR
DATA
RECOVERY
CH0
8
VSYNC
HSYNC
DE0
CLT1
CLT2
CLT3
RXC+
RXC-
VCR
PLL
DIFFERENTIAL SIGNAL
www.datasheet4u.com
MISC.
Subject to Change without Notice
1 page  
Silicon Image, Inc.
SiI141
SiI/DS-0004-D
Output Pin Description
Pin Name
Q35 – Q0
Pin #
See
SiI141
Pin
Diagram
Type
Out
ODCK
DE
HSYNC
VSYNC
CTL1
CTL2
CTL3
36 Out
41 Out
12 Out
14 Out
8 Out
9 Out
10 Out
Description
Output Data [35:0].
Output data is synchronized with output data clock (ODCK).
When PIXS is low Q35-Q24 are low and Q23-Q0 output 24-bit/pixel data.
When PIXS is high Q17-Q0 output the even numbered pixels (pixel 0, 2, 4, ... , etc.) and Q35-Q18 output the
odd numbered pixels (pixel 1, 3, 5, ... , etc.).
Refer to the TFT Signal Mapping (SiI/AN-0008) and DSTN Signal Mapping (SiI/AN-0007) application notes
which tabulate the relationship between the input data to the transmitter and output data from the receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
Output Data Clock.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
Output Data Enable.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This pin is not controlled by PDO.
General output control signal 2
General output control signal 3.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
Configuration Pin Description
Pin Name
OCK_INV
Pin #
80
Type
In
Description
ODCK Polarity. A low level selects normal ODCK output, which enables data latching on the falling edge. A high
level (3.3V) selects inverted ODCK output, which enables data latching on the rising edge. Both conditions are for
color TFT panel support. For color 24-bit DSTN panel support, please refer to the DSTN Signal Mapping
(SiI/AN-0008-A) application note.
PIXS
DF0
ST
5 In Pixel Select. A low level indicates that output data is one pixel (up to 24-bit) per clock and a high level (3.3V)
indicates that output data is two pixels (up to 36-bit) per clock.
6 In Output Data Format. This pin controls clock and data output format. A low level indicates that ODCK runs
continuously for color TFT panel support and a high level (3.3V) indicates that ODCK is stopped (LOW) for color
24-bit DSTN panel support when DE is low. Refer to the TFT Signal Mapping (SiI/AN-0007-A) and DSTN
Signal Mapping (SiI/AN-0008-A) application notes for a table on TFT or DSTN panel support.
79 In Output Driver Strength. A low level indicates low drive. A high level indicates high drive.
Power Management Pin Description
Pin Name
SCDT
PD
PDO
Pin #
7
2
3
Type
Out
In
In
Description
SyncDetect. A high level is output when DE is toggling. A low level is output when DE is inactive.
Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down
mode. During power down mode all internal circuitry is powered down and digital I/O are set the same as when
PDO is asserted. (see PDO pin description).
Power Down Output (active low). A high level indicates normal operation. A low level puts the output drivers only into
a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. There is an
internal pull-up resistor on PDO that defaults the chip to normal operation if left unconnected. SCDT and CTL1 are
not tri-stated by this pin.
Differential Signal Data Pin Description
Pin Name
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RXC+
RXC-
EXT_RES
Pin #
70
71
67
68
64
65
74
73
76
Type Description
Analog TMDS Low Voltage Differential Signal input data pairs.
Analog TMDS Low Voltage Differential Signal input clock pair.
Analog Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable. In the
common case of 50Ω transmission line, an external 500Ω resistor must be connected between AVCC and this
pin.
5 Subject to Change without Notice
5 Page | ||
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| PDF Descargar | [ Datasheet SII141.PDF ] | |
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