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STP14NF12 の電気的特性と機能

STP14NF12のメーカーはST Microelectronicsです、この部品の機能は「N-CHANNEL Power MOSFET」です。


製品の詳細 ( Datasheet PDF )

部品番号 STP14NF12
部品説明 N-CHANNEL Power MOSFET
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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STP14NF12 Datasheet, STP14NF12 PDF,ピン配置, 機能
STP14NF12
STP14NF12FP
N-CHANNEL 120V - 0.16- 14A TO-220/TO-220FP
LOW GATE CHARGE STripFET™ POWER MOSFET
TYPE
VDSS
RDS(on)
STP14NF12
STP14NF12FP
120 V
120 V
< 0.18
< 0.18
s TYPICAL RDS(on) = 0.16
s EXCEPTIONAL dv/dt CAPABILITY
s APPLICATION ORIENTED
CHARACTERIZATION
ID
14 A
14 A
DESCRIPTION
This Power MOSFET series realized with STMicro-
electronics unique STripFET process has specifical-
ly been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated DC-DC
converters for Telecom and Computer application. It
is also intended for any application with low gate
charge drive requirements
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s HIGH-EFFICIENCY DC-DC CONVERTERS
s UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR
Drain-gate Voltage (RGS = 20 k)
VGS Gate- source Voltage
ID Drain Current (continuous) at TC = 25°C
ID Drain Current (continuous) at TC = 100°C
IDM ( ) Drain Current (pulsed)
PTOT
Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
EAS (2) Single Pulse Avalanche Energy
VISO
Insulation Withstand Voltage (DC)
Tj Operating Junction Temperature
Tstg Storage Temperature
(q) Pulse width limited by safe operating area
August 2002
Value
STP14NF12 STP14NF12FP
120
120
±20
14 8.5
96
56 34
60 25
0.4 0.17
9
60
- 2500
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
V
-55 to 175
°C
(1) ISD 14A, di/dt 300A/µs, VDD V(BR)DSS, Tj TJMAX.
(2) Starting Tj = 25°C, ID = 14A, VDD = 50V
1/9

1 Page





STP14NF12 pdf, ピン配列
STP14NF12/STP14NF12FP
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
Parameter
Test Conditions
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 50 V, ID = 7 A
RG = 4.7VGS = 10V
(Resistive Load, see Figure 3)
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VDD = 80 V, ID = 14 A,
VGS = 10V
Min.
Typ.
16
25
15.5
3.7
4.7
Max.
21
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
Symbol
Parameter
td(off)
tf
Turn-off-Delay Time
Fall Time
Test Conditions
VDD = 50 V, ID = 7 A,
RG = 4.7Ω, VGS = 10V
(Resistive Load, see Figure 3)
Min.
Typ.
32
8
Max.
Unit
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
ISD Source-drain Current
ISDM (2) Source-drain Current (pulsed)
VSD (1) Forward On Voltage
ISD = 14 A, VGS = 0
trr
Qrr
IRRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 14 A, di/dt = 100A/µs,
VDD = 50 V, Tj = 150°C
(see test circuit, Figure 5)
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Min.
Typ.
92
230
5
Max.
14
56
1.5
Unit
A
A
V
ns
nC
A
Safe Operating Area For TO-220
Safe Operating Area For TO-220FP
3/9


3Pages


STP14NF12 電子部品, 半導体
STP14NF12/STP14NF12FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9

6 Page



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共有リンク

Link :


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