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PDF MT5C6404 Data sheet ( Hoja de datos )
| Número de pieza | MT5C6404 | |
| Descripción | 16K x 4 SRAM SRAM MEMORY ARRAY | |
| Fabricantes | ASI | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SRAM
MT5C6404
16K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-86859
• SMD 5962-89692
• MIL-STD-883
FEATURES
• Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-12
-15
-20
-25
-35
-45*
-55*
-70*
• Package(s)
Ceramic DIP (300 mil) C No. 105
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 35ns
access devices.
PIN ASSIGNMENT
(Top View)
22-Pin DIP (C)
(300 MIL)
A5 1
A6 2
A7 3
A8 4
A9 5
A10 6
A11 7
A12 8
A13 9
CE\ 10
Vss 11
22 Vcc
21 A4
20 A3
19 A2
18 A1
17 A0
16 DQ4
15 DQ3
14 DQ2
13 DQ1
12 WE\
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications, Austin
Semiconductor offers chip enable (CE\) on all organizations.
This enhancement can place the outputs in High-Z for
additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ goes LOW.
The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C6404
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
ACTEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
Q
255
SRAM
MT5C6404
+5V
480
30pF
Q
255
+5V
480
5 pF
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is sampled.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tHZCE and tHZWE are specified with CL = 5pF as in
Fig. 2. Transition is measured ±500mV typical from steady
state voltage, allowing for actual tester RC time constant.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = READ Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM MIN MAX UNITS NOTES
VCC for Retention Data
VDR
2
---
V
Data Retention Current
CE\ > (VCC - 0.2V) VCC = 2V ICCDR --- 300 µA
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 3V ICCDR --- 500 µA
Chip Deselect to Data
Retention Time
tCDR
0
---
ns
4
Operation Recovery Time
tR tRC ---
ns 4, 11
MT5C6404
Rev. 1.0 9/01
LOW Vcc DATA RETENTION WAVEFORM
VCC
tCDR
CE\
VIH
VIL
111122223333444455556666777788889999
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
VDR
tR
111122223333444455556666111177772111122288883222233343343344
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MT5C6404.PDF ] | |
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