DataSheet.jp

ST24C01R の電気的特性と機能

ST24C01RのメーカーはST Microelectronicsです、この部品の機能は「(ST2xxx) SERIAL 1K 128 x 8 EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST24C01R
部品説明 (ST2xxx) SERIAL 1K 128 x 8 EEPROM
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




このページの下部にプレビューとST24C01Rダウンロード(pdfファイル)リンクがあります。

Total 16 pages

No Preview Available !

ST24C01R Datasheet, ST24C01R PDF,ピン配置, 機能
ST24/25C01, ST24C01R
ST24/25W01
SERIAL 1K (128 x 8) EEPROM
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x01 versions
– 2.5V to 5.5V for ST25x01 versions
– 1.8V to 5.5V for ST24C01R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W01 and ST25W01
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ST24C/W01 are replaced by the M24C01
ST25C/W01 are replaced by the M24C01-W
ST24C01R is replaced by the M24C01-R
DESCRIPTION
This specification covers a range of 1K bits I2C bus
EEPROM products, the ST24/25C01, the
ST24C01R and the ST24/25W01. In the text, prod-
ucts are referred to as ST24/25x01, where "x" is:
"C" for Standard version and "W" for hardware
Write Control version.
Table 1. Signal Names
E0-E2
SDA
SCL
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
MODE
WC
Multibyte/Page Write Mode
(C version)
Write Control (W version)
VCC Supply Voltage
VSS Ground
NOT FOR NEW DESIGN
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
MODE/WC*
ST24x01
ST25x01
ST24C01R
SDA
VSS
AI00839D
Note: WC signal is only available for ST24/25W01 products.
November 1997
This is information on a product still in production but not recommended for new design
1/16

1 Page





ST24C01R pdf, ピン配列
Table 3. Device Select Code
Bit b7
Device Select
1
Note: The MSB b7 is sent first.
Device Code
b6 b5
01
ST24/25C01, ST24C01R, ST24/25W01
Chip Enable
RW
b4 b3 b2 b1 b0
0 E2 E1 E0 RW
Table 4. Operating Modes (1)
Mode
RW bit
MODE
Current Address Read
’1’
X
Random Address Read
’0’
’1’
X
Sequential Read
’1’ X
Byte Write
Multibyte Write (2)
’0’ X
’0’ VIH
Page Write
’0’ VIL
Notes: 1. X = VIH or VIL
2. Multibyte Write not available in ST24/25W01 versions.
Bytes
1
1
1 to 128
1
4
8
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Similar to Current or Random Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. Aresistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to VCC or VSS to
establish the device select code.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W01 and
ST25W01 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL and
the memory area is not write protected.
3/16


3Pages


ST24C01R 電子部品, 半導体
ST24/25C01, ST24C01R, ST24/25W01
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol
Alt
Parameter
Min Max Unit
tCH1CH2
tR Clock Rise Time
1 µs
tCL1CL2
tDH1DH2
tF Clock Fall Time
tR Input Rise Time
300 ns
1 µs
tDL1DL1
tCHDX (1)
tCHCL
tDLCL
tCLDX
tCLCH
tF
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
Input Fall Time
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
300 ns
4.7 µs
4 µs
4 µs
0 µs
4.7 µs
tDXCX
tCHDH
tDHDL
tCLQV (2)
tSU:DAT
tSU:STO
tBUF
tAA
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
250 ns
4.7 µs
4.7 µs
0.3 3.5 µs
tCLQX
tDH Data Out Hold Time
300 ns
fC fSCL Clock Frequency
100 kHz
tW (3)
tWR Write Time
10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION (cont’d)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
1K memories can be connected on the same bus
giving a memory capacity total of 8K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
6/16

6 Page



ページ 合計 : 16 ページ
 
PDF
ダウンロード
[ ST24C01R データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ST24C01

SERIAL 1K 128 x 8 EEPROM

ST Microelectronics
ST Microelectronics
ST24C01

(ST2xxx) SERIAL 1K 128 x 8 EEPROM

ST Microelectronics
ST Microelectronics
ST24C01R

(ST2xxx) SERIAL 1K 128 x 8 EEPROM

ST Microelectronics
ST Microelectronics


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap