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SD1010D の電気的特性と機能

SD1010DのメーカーはSmartASICです、この部品の機能は「Digital Interface XGA TFT LCD Display Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 SD1010D
部品説明 Digital Interface XGA TFT LCD Display Controller
メーカ SmartASIC
ロゴ SmartASIC ロゴ 




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SD1010D Datasheet, SD1010D PDF,ピン配置, 機能
SD1010D - Digital-Interface XGA TFT LCD Display Controller
Data Sheet
SD1010D
Digital-Interface XGA TFT
LCD Display Controller
February 2000
525 Race Street, Suite 250, San Jose, CA 95126, USA.
Main: (408) 283-5098 Fax: (408) 283-5099

1 Page





SD1010D pdf, ピン配列
SmartASIC, Inc. reserves the right to change or modify the information
cOonVtaEinRedVhIeEreWin without notice. It is the customer’s responsibility to ensure
he/she has the most recent revision of the user guide. SmartASIC, Inc. makes
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oXrGomAiTssFioTnLs,CwDhimchonmitaoyrsa.pApedairgiintalt-hiinstedrofcaucme LenCtD. monitor takes digital RGB signals from a
graphic card of a personal computer, the exact same input interface as a conventional CRT
monitor. This feature makes digital-interface LCD monitor a true replacement of a conventional
CRT monitor.
The digital input RGB signals are first received by TMDS receiver, and the 24-bit RGB data are then fed into
the SD1010D. The SD1010D is capable of performing automatic detection of the display resolution and timing
of input signals generated from various PC graphic cards. No special driver is required for the timing detection,
nor any manual adjustment. The SD1010D then automatically scales the input image to fill the full screen of the
LCD monitor. The SD1010D can interface with TFT LCD panels from various manufacturers by generating
either 24-bit or 48-bit RGB signal to the LCD panel based upon the timing parameters saved in the EEPROM.
The SD1010D implements four advanced display technologies:
1. Advanced mode detection without any external CPU assist
2. Advanced programmable interpolation algorithm
3. Stand-alone mode support, and
4. Advanced true color support with both dithering and frame modulation.
The SD1010D also provides distinguished system features to the TFT LCD monitor solution.
The first one is “plug-and-play”, and the second one is “cost-effective system solution”. To be
truly plug-and-display, the SD1010D performs automatic input mode detection. Furthermore,
the SD1010D can generate output video even when the input signal is beyond the specifications
or no input signal is fed.
For “cost-effective system solution”, the SD1010D implements many system support features
such as OSD mixer, error status indicators, 2-wire serial interface for both EEPROM and host
CPU interface, and low-cost IC package. Another important contributing factor is that the
SD1010D does not require external frame buffer memory for the automatic image scaling and
synchronization.
Figure 1 shows the block diagram of the SD1010D as well as the connections of important
system components around the SD1010D.
525 Race Street, Suite 250, San Jose, CA 95126, USA.
Main: (408) 283-5098 Fax: (408) 283-5099


3Pages


SD1010D 電子部品, 半導体
Table 1: SD1010 pin description (sorted by pin number)
Symbol
ROM_SCL
ROM_SDA
GND
CPU_SCL
CPU_SDA
PWM_CTL
CLK_1M
VDD
CLK_1M_O
RESET_B
R_OSD
G_OSD
B_OSD
EN_OSD
SCAN_EN
TEST_EN
FCLK0
VCLK0
FCLK1
VCLK1
HSYNC_O
VSYNC_O
DCLK_OUT
DE_OUT
GND
VDD
R_OUT0_E
R_OUT1_E
R_OUT2_E
R_OUT3_E
HSYNC_X
R_OUT4_E
R_OUT5_E
R_OUT6_E
R_OUT7_E
GND
R_OUT0_O
R_OUT1_O
R_OUT2_O
R_OUT3_O
VDD
R_OUT4_O
R_OUT5_O
R_OUT6_O
PIN Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O Description
O SCL in I2C for EEPROM interface
I/O SDA in I2C for EEPROM interface
Ground
I SCL in I2C for CPU interface
I/O SDA in I2C for CPU interface
O PWM control signal (not used)
I Free Running Clock (default: 1MHz)
Power Supply
O Feedback of free Running Clock
I System Reset ( active LOW)
I OSD Color Red
I OSD Color Green
I OSD Color Blue
I OSD Mixer Enable
=0, No OSD output
=1,R_OUT[7:0]= {R_OSD repeat 8 times}
G_OUT[7:0]= {G_OSD repeat 8 times }
B_OUT[7:0]= {B_OSD repeat 8 times }
I Manufacturing test pin (NC)
I Manufacturing test pin (NC)
O Input PLL Feedback Clock (not used)
I Input Clock 0 (not used)
O Output PLL Feedback Clock
I Output PLL Output Clock
O Output HSYNC (the polarity is programmable through
CPU, default is active low)
O Output VSYNC (the polarity is programmable through
CPU, default is active low)
O Output Clock to Control Panel (the polarity is
programmable through CPU)
O Output Display Enable for Panel (the polarity is
programmable through CPU, default is active HIGH)
Ground
Power Supply
O Output Color Red Even Pixel (left pixel)
O Output Color Red Even Pixel (left pixel)
O Output Color Red Even Pixel (left pixel)
O Output Color Red Even Pixel (left pixel)
O Default HSYNC generated by ASIC (active LOW)
O Output Color Red Even Pixel (left pixel)
O Output Color Red Even Pixel (left pixel)
O Output Color Red Even Pixel (left pixel)
O Output Color Red Even Pixel (left pixel)
Ground
O Output Color Red Odd Pixel (right pixel)
O Output Color Red Odd Pixel (right pixel)
O Output Color Red Odd Pixel (right pixel)
O Output Color Red Odd Pixel (right pixel)
Power Supply
O Output Color Red Odd Pixel (right pixel)
O Output Color Red Odd Pixel (right pixel)
O Output Color Red Odd Pixel (right pixel)
525 Race Street, Suite 250, San Jose, CA 95126, USA.
Main: (408) 283-5098 Fax: (408) 283-5099

6 Page



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