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S3067TB20 の電気的特性と機能

S3067TB20のメーカーはApplied Micro Circuitsです、この部品の機能は「Multirate Sonet / SDH / ATM Transceiver w/FEC」です。


製品の詳細 ( Datasheet PDF )

部品番号 S3067TB20
部品説明 Multirate Sonet / SDH / ATM Transceiver w/FEC
メーカ Applied Micro Circuits
ロゴ Applied Micro Circuits ロゴ 




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S3067TB20 Datasheet, S3067TB20 PDF,ピン配置, 機能
DEVICE
SMPUELCTIFIIRCAATTIEON(OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SMBOUiCNLMETIOTR/SASDTLEHVP/(AOETCCM-L48OC/C2L4-O1/1C22K/3T/GRGEABNEES/FRMCAI)TTSTOOERNREATN/SDDRHE/ACTEMIVTERRANSCEIVER w/ FEC
®
S3067
SS33006677
FEATURES
• SiGe BiCMOS technology
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLL for clock generation
• Supports:
- OC-48 (with FEC)
- OC-24 (with FEC)
- OC-12 (with FEC)
- OC-3 (with FEC)
- Fibre Channel
• FEC capability up to 8 bytes per 255-byte block
• Reference frequency – 131.25 MHz to 178 MHz
• Interface to LVPECL and TTL logic
• 16-Bit single-ended LVPECL data path
• Compact 156 Pin TBGA package
• Diagnostic loopback mode
• Supports line timing
• Lock Detect
• Signal detect input
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3 V supply
• Typical power 1.5 W
APPLICATIONS
• Wavelength Division Multiplexing equipment
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
GENERAL DESCRIPTION
The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization SO-
NET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
131.25 MHz to 178 MHz reference clock in support
of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3067 is pack-
aged in a 156 Pin TBGA, offering designers a small
package outline.
The S3067 supports FEC designs with internal divid-
ers or external clocking modes.
Figure 1. System Block Diagram
2.488 Gbps
X
S3076
Clock
Recovery
Unit
2.488
Gbps
X
PERFORMANCE MONITOR
S3067
155 Mbps
Receive
Deserialization
X
S3062
Receive
S3062 167 Mbps S3067 2.67 Gbps
Transmit
FEC Added
X+Y
Transmit
Serialization X + Y
E/O
OPTICAL FIBER
PERFORMANCE MONITOR
O/E
S3076
S3067
S3062
Clock 2.67 Gbps Receive
167 Mbps Receive
Recovery X + Y Deserialization X + Y FEC Data
Unit Stripped Off
S3062
Transmit
155 Mbps
S3067
Transmit
2.488 Gbps
X Serialization X
X = Data
Y = FEC Data
September 17, 2002/ Revision A
1

1 Page





S3067TB20 pdf, ピン配列
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067
S3067 OVERVIEW
The S3067 transceiver implements SONET/SDH
and WDM serialization/deserialization, and transmis-
sion functions. The block diagram in Figure 4 shows
the basic operation of the chip. This chip can be
used to implement the front end of WDM equipment,
which consists primarily of the serial transmit inter-
face and the serial receive interface. The chip
handles all the functions of these two elements, in-
cluding parallel-to-serial and serial-to-parallel
conversion, clock generation, and system timing.
The system timing circuitry consists of management
of the data stream and clock distribution throughout
the front end.
S3067 has the ability to bypass the internal VCO
with an external source and also with the receive
clock. The device generates 14/15, 15/14, 16/17 and
17/16 clocks based upon the received clock and an
external clock to incorporate the FEC capability. The
dividers support the first two rates shown in Table 4.
The S3067 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Table 2. Data Rate Select
RATESEL 0 RATESEL 1 Operating Mode
0 0 OC-3
0 1 OC-12
1 0 OC-24/GBE/FC
1 1 OC-48
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. S3067 Supports six different code
rates, besides the normal rate, for each of the four
operating modes.
Suggested Interface Devices
AMCC S3076 OC-48 Clock Recovery Device
AMCC S3062 OC-48 Performance Monitor
Table 3. FEC Select
FEC 0
1
2
0 01
1 01
0 11
1 11
0 00
1 00
0 10
1 10
VCO
Divider
17
16
15
14
17
16
15
14
RSCLK
Divider
16
17
14
15
X
X
X
X
Table 4. FEC Modes
Error Correcting Capability
Code Rate showing
Bandwidth Expansion due
to code words & FSB
Example of increased input clock
frequency for STS-48/STM-16 (MHz)
8 bytes per 255-byte block
255/238 = 7.14% increase
155.52*255/238 = 155.52 * 15/14 = 166.63
7 bytes per 255-byte block
255/240 = 6.25% increase
155.52*255/240 = 155.52 * 17/16 = 165.24
6 bytes per 255-byte block
255/242 = 5.37% increase
155.52*255/242 = 163.87
5 bytes per 255-byte block
255/244 = 4.51% increase
155.52*255/244 = 162.53
4 bytes per 255-byte block
255/246 = 3.66% increase
155.52*255/246 = 155.52 * 85/82 = 161.21
3 bytes per 255-byte block
255/248 = 2.82% increase
155.52*255/248 = 159.91
September 17, 2002/ Revision A
3


3Pages


S3067TB20 電子部品, 半導体
S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067 TRANSCEIVER
FUNCTIONAL DESCRIPTION
Transmitter Operation
The S3067 transceiver chip performs the serialization
stage in the processing of a transmit SONET STS-48/
STS-24/STS-12/STS-3/GBE/FC data stream depend-
ing on the data rate selected. It converts 16-bit
parallel data to bit serial format.
A high-frequency bit clock can be generated from a
131.25 MHz to 178 MHz frequency reference by us-
ing an integral frequency synthesizer consisting of a
phase-locked loop circuit with a divider in the loop.
Diagnostic loopback (transmitter to receiver) and line
loopback (receiver to transmitter) is provided. See
Other Operating Modes.
The bypass signal selects between the BYPASSCLK
and the VCO clock. BYPASSCLK can be used to pro-
vide an alternative clock to the internal VCO when the
user selects an error correcting capability which is not
provided by the S3067 dividers. The user must pro-
vide the required frequency for the BYPASSCLK
when error-correcting capability of 6/5/4/3 bytes per
255-byte block is selected.
Clock Synthesizer
The clock synthesizer, shown in the block diagrams
of Figures 4 and 5, is a monolithic PLL that gener-
ates the serial output clock frequency locked to the
input Reference Clock (REFCLKP/N).
The REFCLKP/N input must be generated from a
crystal oscillator that has a frequency accuracy bet-
ter than the value stated in Table 10 in order for the
TSCLK frequency to have the accuracy required for
operation in a SONET system. Lower-accuracy crys-
tal oscillators may be used in applications less
demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
The divide by ‘N’ and divide by ‘M’ provide the
counters required to support error correcting capabil-
ity. The values of ‘N’ and ‘M’ can be selected by
FECSEL lines.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The timing generation function, seen in Figure 4,
provides a divide-by-16 version of the transmit serial
clock. This circuitry also provides an internally gen-
erated load signal, which transfers the PIN[15:0]
data from the parallel input register to the serial shift
register.
The PCLK output is a divide-by-16 rate version of
transmit serial clock (divide-by-16). PCLK is in-
tended for use as a divide-by-16 clock for upstream
multiplexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3067 device.
The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the reference clock REFCLK. The PLL in
the clock synthesizer maintains the stability of the
synthesized clock by comparing the phase of the
internal clock with that of the Reference Clock
(REFCLK).
Table 5. Reference Jitter Limits
Operating Mode Band Width RMS Jitter
STS-48
12 kHz to 20 MHz -61 dBc
STS-24
12 kHz to 10 MHz 2 ps
STS-12
12 kHz to 5 MHz 4 ps
STS-3
12 kHz to 1 MHz 16 ps
6 September 17, 2002/ Revision A

6 Page



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部品番号部品説明メーカ
S3067TB20

Multirate Sonet / SDH / ATM Transceiver w/FEC

Applied Micro Circuits
Applied Micro Circuits


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