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PDF VSC9182 Data sheet ( Hoja de datos )
| Número de pieza | VSC9182 | |
| Descripción | Telecomm / Datacomm | |
| Fabricantes | Vitesse Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VSC9182 (archivo pdf) en la parte inferior de esta página. Total 2 Páginas | ||
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TIPMHESYTSRIECAAML®L APYROEDRUPCRT OFADMUICLYT
VSC9182
VSC9182 - 40G STS-1 Time Slot Interchange
FEATURES:
Interconnection Matrix
!Time & Space Switches any STS-(n) [n= 1, 3c, 12c] Signal of an
Incoming STS-12 into any Byte Position of any STS-12 Output
!Single Stage Non-blocking Structure of the Switch Allows for
Multicast and Full Broadcast
!Hitless Switching: Programming is Queued and Takes Effect
After user Intervention During the Next Frame Boundary
!Unequipped or AIS Signals can be Substituted into any of the
Outgoing STS-1 Timeslots.
!Provides a Capability to Read out the Switch Configuration
(address map)
Input Backplane Interface
!Serial 622.08 Mb/s Differential LVDS STS-12/STM-4 Inputs
!Receives 64 Serial 622.08 Mb/s STS-12/STM-4 Signals
!Input Signals are Presumed Frequency Synchronous and Frame
aligned to Within +/- 3 Time Slots of the System SYNC Input
!Provides On-chip Data Recovery De-skewing Functionality to
Bit-align, Byte-align and Frame-align all Incoming STS-12s
(Within the above Tolerance) to the Local Clock
!Flags Out-of-frame (OOF), Loss-of-signal (LOS) and Parity Errors
!Checks B1 Parity of Incoming Data
!Inserts Unequipped or AIS When Channel is in OOF, LOS or
Unprovisioned State and Inhibits Alarms
!Optionally De-scrambles Incoming SONET Data
Output Backplane Interface
!Serial 622.08 Mb/s Differential LVDS STS-12/STM-4 Outputs
!Optionally Inserts Byte-interleaved Parity into B1 Byte of
Following Frame
!Optionally Scrambles Outgoing SONET Data
!Optionally Inserts AIS or Unequipped on a Per-channel, Per-
time-slot Basis
CPU Interface
!Generic Microprocessor (CPU) Interface used for Device
Configuration and Status Checking
!10-bit Data Bus and 11-bit Address Bus
!Interrupt Output Pin to Signal Status Changes of Internal Alarms
Test Interface
!IEEE P1149.1 Test Access Port Controls External Boundary Scan
TIMESTREAM DIAGRAM:
4 x OC-48
1 x OC-192
VSC9186 10Gb/s 2.5Gb/s
Pointer Processor
PHY's & Analog
VSC9187/88
VT/TU Switch
2.5Gb/s
Ethernet
PHY, MAC,
Packet µP
CSIX
2.5Gb/s
SONET/SDH Framer
(STS3c) - STS48c)
Packet/Cell µP
CSIX
2.5Gb/s
SONET/SDH Framer
(STS48c - STS-768c)
Packet/Cell µP
CSIX
DS-3
T1/E1
T1/E1/DS-3 Term
DS-0/DS-1/DS-3 2.5Gb/s
HDLC & M13
CSIX
PB-VSC9182-001
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet VSC9182.PDF ] | |
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