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I.MX31 の電気的特性と機能

I.MX31のメーカーはFreescale Semiconductorです、この部品の機能は「Multimedia Applications Processors」です。


製品の詳細 ( Datasheet PDF )

部品番号 I.MX31
部品説明 Multimedia Applications Processors
メーカ Freescale Semiconductor
ロゴ Freescale Semiconductor ロゴ 




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I.MX31 Datasheet, I.MX31 PDF,ピン配置, 機能
Freescale Semiconductor
Product Brief
Document Number: MC1128MX31PB
Rev. 0.6, 06/2005
i.MX31 and i.MX31L
Multimedia Applications Processors
1 Introduction
The i.MX31 and i.MX31L multimedia applications
processors represent Freescale Semiconductor’s latest
achievement in multimedia integrated applications
processors that are part of a growing family of
multimedia-focused products offering high performance
processing optimized for lowest power consumption.
The i.MX31 and i.MX31L processors feature Freescale's
advanced and power-efficient implementation of the
ARM1136JF-S™ core, which operates at speeds starting
at 532 MHz.
Unless otherwise specified, the material in this product
brief is applicable to both the i.MX31 and i.MX31L
processors. Features include the following:
Smart Speed Technology—The heart of the
i.MX31 and i.MX31L processors is a level of
power management throughout the ICs that allow
the rich suite of multimedia features and
peripherals to achieve minimum system power
consumption in both active and various
low-power modes. Smart Speed Technology
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
© Freescale Semiconductor, Inc., 2005. All rights reserved.

1 Page





I.MX31 pdf, ピン配列
Features
Connectivity
Internal
3 x CSPI
2 x SSI/I2S
3 x I2C
AUDMUX
External
5 x UART
USB OTG HS
2 x USB Host
1-Wire
Fast IrDA
Expansion
2 x MMC/SD
PCMCIA/CF
2 x Memory
Stick - Pro
SIM
ATA
CPU Complex
ARM1136TM CPU
Smart Speed
Switch (MAX)
I-Cache
D-Cache
L2-Cache
ROM
Patch
ETM
Vector Floating
Processor
Special
Functions
Security HW
Memory
Interface
SDRAM/DDR
NANDF Ctl
PSRAM
SmartMedia
Std System I/O
eDMA
3 x Timers
PWM
WD Timer
RTC
GPIO
RAM, ROM
System Control
JTAG, ETM
Bootstrap
System Reset
PLL &
Power Mgmt
Multimedia &
Human Interface
Graphics
Accelerator*
MPEG-4
Encoder
Keypad
Image
Processing Unit
Inversion and
Rotation
Camera I/F
Blending
Display/TV Ctl
Pre & Post
Processing
* Not available in i.MX31L
Figure 1. i.MX31 and i.MX31L Functional Block Diagram
2.1 ARM11™ Platform
The ARM11™ platform consists of the ARM1136JF-S processor, a level 2 (L2) cache system, 6 × 5
multi-layer AHB 2.v6 Smart Speed Crossbar Switch (MAX), L2 memory system, and an ARM11 vectored
interrupt controller (AVIC).
In addition, the ARM11 platform contains the Embedded Trace Kit™ (ETK) from ARM Ltd. These
modules consist of the Embedded Trace Macrocell™ (ETM™), the Embedded Trace Buffer™ (ETB™),
and the Cross Trigger Interface (CTI) module.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
Freescale Semiconductor
3


3Pages


I.MX31 電子部品, 半導体
Features
2.4.1 Video Applications
The i.MX31 and i.MX31L processors are optimized to support a variety of video applications. Figure 2 on
page 6 describes the video processing chain and its implementation.
Image Sensor
Display
Performed by:
Camera (Image Signal Processing)
(or ARM11 SW)
Image Processing Unit in i.MX31
MPEG4 Encoder in i.MX31
ARM11 SW
Image Conversion:
• Resizing (resolution adjustment)
• Rotation & Inversion
• Pixel format conversion
(color space, packing, …)
• Combining with a graphics overlay
Bayer
Format
Conversion
YUV
Quality
Enhancement
Image
Conversion
Image
Processing
Unit
(IPU)
Viewfinder Window
Compression
MPEG-4
Encoder
Memory
Combining
with Audio
Communication
Network
Figure 2. Video Processing Chain
RGB
Image
Conversion
Post Filtering
YUV
De-compression
Separation
from Audio
The video implementation in the i.MX31 and i.MX31L processors is a result of a smart trade-off between
performance and flexibility. The following points describe some of the video performance features:
Image processing—The processing required for a camera preview function is performed fully in
hardware, allowing the CPU to be powered-down in this stage.
Encoding—MPEG-4 SP and the H.263 baseline formats are fully hardware accelerated,
supporting resolutions up to VGA at 30 fps. As a result, a high degree of power efficiency is
achieved, and the CPU is freed to perform other tasks. Encoding for other video standards are
achieved using software implementation.
Decoding—Based on a mixture of software and hardware, this implementation provides the
greatest flexibility to support a variety of algorithms and future extensions. A sufficient software
optimization level may be achieved using the advanced ARM11 instruction set and multi-level
cache system. For MPEG4, the post-filtering (de-blocking and de-ringing) is accelerated by IPU
hardware, resulting in a 75% load reduction on the ARM11 core. For H.264 baseline format—the
most processing-intensive format—the deblocking filter is also performed in hardware providing
a 30% acceleration improvement The powerful ARM11 processor (including its 2-level cache
system) provides the flexibility to decode at a high rate any currently relevant formats (up to HVGA
@ 30 fps), as well as possible future extensions.
i.MX31 and i.MX31L Multimedia Applications Processors Product Brief, Rev. 0.6
6 Freescale Semiconductor

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
I.MX31

Multimedia Applications Processors

Freescale Semiconductor
Freescale Semiconductor
I.MX31L

Multimedia Applications Processors

Freescale Semiconductor
Freescale Semiconductor
i.MX35

Applications Processors

Freescale Semiconductor
Freescale Semiconductor


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