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STE53NA50のメーカーはST Microelectronicsです、この部品の機能は「N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR」です。 |
部品番号 | STE53NA50 |
| |
部品説明 | N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR | ||
メーカ | ST Microelectronics | ||
ロゴ | |||
このページの下部にプレビューとSTE53NA50ダウンロード(pdfファイル)リンクがあります。 Total 7 pages
STE53NA50
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
ST E53NA50
VDSS
500 V
RDS(on)
< 0.085 Ω
ID
53 A
s TYPICAL RDS(on) = 0.075 Ω
s HIGH CURRENT POWER MODULE
s AVALANCHE RUGGED TECHNOLOGY
s VERY LARGE SOA - LARGE PEAK POWER
CAPABILITY
s EASY TO MOUNT
s SAME CURRENT CAPABILITY FOR THE
TWO SOURCE TERMINALS
s EXTREMELY LOW Rth (Junction to case)
s VERY LOW INTERNAL PARASITIC
INDUCTANCE
s ISOLATED PACKAGE UL RECOGNIZED
APPLICATIONS
s SMPS & UPS
s MOTOR CONTROL
s WELDING EQUIPMENT
s OUTPUT STAGE FOR PWM, ULTRASONIC
CIRCUITS
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
V D GR
V GS
ID
ID
Drain- gate Voltage (RGS = 20 kΩ)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
IDM(•) Drain Current (pulsed)
Pto t Total Dissipation at Tc = 25 oC
Derating Factor
Tst g St orage Temperature
Tj Max. Operating Junction Temperature
VISO Insulation Withhstand Voltage (AC-RMS)
(•) Pulse width limited by safe operating area
February 1998
Va l u e
500
500
± 30
53
33
212
460
3.68
-55 to 150
150
2500
Unit
V
V
V
A
A
A
W
W/oC
oC
oC
V
1/7
1 Page STE53NA50
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
S ymb ol
td(on)
tr
P a ra m et er
Turn-on Time
Rise Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
Test Conditions
VDD = 250 V ID = 27 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 1)
VDD = 400 V ID = 53 A VGS = 10 V
Min.
Typ .
57
92
Max.
80
130
470 658
54
219
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
S ymb ol
tr(Vo f f)
tf
tc
P a ra m et er
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 400 V
ID = 53 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 3)
Min.
Typ .
105
36
145
Max.
145
50
205
Unit
ns
ns
ns
SOURCE DRAIN DIODE
S ymb ol
P a ra m et er
Test Conditions
ISD
ISDM (•)
Source-drain Current
Source-drain Current
(pulsed)
VSD (∗) Forward On Voltage
ISD = 53 A
VGS = 0
trr Reverse Recovery
Time
Qrr Reverse Recovery
ISD = 53 A di/dt = 100 A/µs
VR = 100 V Tj = 150 oC
(see test circuit, figure 3)
Charge
IRRM Reverse Recovery
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ .
Max.
53
212
Unit
A
A
1000
31.5
63
1.6
V
ns
µC
A
Safe Operating Area for
Thermal Impedance
3/7
3Pages STE53NA50
DIM.
A
B
C
D
E
F
G
H
J
K
L
M
N
O
MIN.
11.8
8.9
1.95
0.75
12.6
25.15
31.5
4
4.1
14.9
30.1
37.8
4
7.8
ISOTOP MECHANICAL DATA
mm
TYP.
MAX.
12.2
9.1
2.05
0.85
12.8
25.5
31.7
4.3
15.1
30.3
38.2
8.2
MIN.
0.466
0.350
0.076
0.029
0.496
0.990
1.240
0.157
0.161
0.586
1.185
1.488
0.157
0.307
inch
TYP.
MAX.
0.480
0.358
0.080
0.033
0.503
1.003
1.248
0.169
0.594
1.193
1.503
0.322
G
O
N
A
B
J
K
L
M
6/7
C
6 Page | |||
ページ | 合計 : 7 ページ | ||
|
PDF ダウンロード | [ STE53NA50 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
STE53NA50 | N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR | ST Microelectronics |
STE53NA50 | Trans MOSFET N-CH 500V 53A 4-Pin ISOTOP | New Jersey Semiconductor |