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MC74AC377 の電気的特性と機能

MC74AC377のメーカーはON Semiconductorです、この部品の機能は「Octal D Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 MC74AC377
部品説明 Octal D Flip-Flop
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




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MC74AC377 Datasheet, MC74AC377 PDF,ピン配置, 機能
MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
MSL = 1 for all Surface Mount
Chip Complexity: 292 FETs or 73 Gates
These are Pb−Free Devices
www.onsemi.com
SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
CE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN NAMES
PIN
D0−D7
CE
Q0−Q7
CP
FUNCTION
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 10
1
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
Publication Order Number:
MC74AC377/D

1 Page





MC74AC377 pdf, ピン配列
MC74AC377, MC74ACT377
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
IGND
TSTG
TL
TJ
qJA
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND) (Note 1)
DC Input Diode Current
DC Output Diode Current
DC Output Sink/Source Current
DC Supply Current, per Output Pin
DC Ground Current, per Output Pin
Storage Temperature Range
Lead temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
SOIC
TSSOP
−0.5 to +7.0
−0.5 to VCC +0.5
−0.5 to VCC +0.5
±20
±50
±50
±50
±100
*65 to )150
260
140
65.8
110.7
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
MSL Moisture Sensitivity
Level 1
FR
VESD
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
UL 94 V−0 @ 0.125 in
> 2000
> 200
> 1000
V
ILatchup Latchup Performance
Above VCC and Below GND at 85_C (Note 6)
±100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IOUT absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
AC
ACT
2.0 5.0 6.0
4.5 5.0 5.5
V
Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND)
0 − VCC V
Input Rise and Fall Time (Note 7)
tr, tf AC Devices except Schmitt Inputs
VCC @ 3.0 V
150
VCC @ 4.5 V
40
− ns/V
VCC @ 5.5 V
25
Input Rise and Fall Time (Note 8)
tr, tf ACT Devices except Schmitt Inputs
VCC @ 4.5 V
10
ns/V
VCC @ 5.5 V
8.0
TA Operating Ambient Temperature Range
−40 25 85 °C
IOH Output Current − High
− − −24 mA
IOL Output Current − Low
− − 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
8. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
www.onsemi.com
3


3Pages


MC74AC377 電子部品, 半導体
MC74AC377, MC74ACT377
SWITCHING WAVEFORMS
tr tf
CLOCK
50%
tw
1/fmax
tPLH
tPHL
Q 50%
Figure 4.
VCC
GND
CE
CLOCK
50%
tsu
th
50%
Figure 5.
VCC
VCC
GND
DATA
CLOCK
VALID
50%
tsu
th
50%
Figure 6.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
OUTPUT
450 W
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
50 W SCOPE
TEST POINT
www.onsemi.com
6

6 Page



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共有リンク

Link :


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