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PDF S29CD016G Data sheet ( Hoja de datos )
| Número de pieza | S29CD016G | |
| Descripción | 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory | |
| Fabricantes | SPANSION | |
| Logotipo |  |
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S29CD016G
16 Megabit (512 K x 32-Bit)
CMOS 2.5 Volt-only Burst Mode, Dual Boot,
Simultaneous Read/Write Flash Memory
Data Sheet
Distinctive Characteristics
Architecture Advantages
Simultaneous Read/Write operations
— Two bank architecture: large bank/ small bank
— Data can be read from bank while executing erase/
program functions in other bank
— Zero latency between read and write operations
User-Defined x32 Data Bus
Dual Boot Block
— Top and bottom boot sectors in the same device
Flexible sector architecture
— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes
sectors
Manufactured on 170 nm process technology
SecSi (Secured Silicon) Sector (256 Bytes)
— Factory locked and identifiable: 16 bytes for secure,
random factory Electronic Serial Number; remainder
may be customer data programmed by Spansion™
— Customer lockable: Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
Programmable Burst interface
— Interface to any high performance processor
— Modes of Burst Read Operation:
— Linear Burst: 4 double words and 8 double words
with wrap around
Program Operation
— Ability to perform synchronous and asynchronous
write operations of burst configuration register
settings independently
Single power supply operation
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
Compatibility with JEDEC standards (JC42.4)
— Software compatible with single-power supply Flash
— Backward-compatible with AMD Am29LV and Am29F
and Fujitsu MBM29LV and MBM29F flash memories
Performance Characteristics
High performance read access
— Initial/random access times as fast as 54 ns
— Burst access time as fast as 9 ns for ball grid array
package
Ultra low power consumption
— Burst Mode Read: 90 mA @ 66 MHz max,
— Program/Erase: 50 mA max
— Standby mode: CMOS: 60 µA max
1 million write cycles per sector typical
20 year data retention typical
VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
— 1.65 V to 2.75 V compatible I/O signals
— 3.6 V tolerant I/O signals
Software Features
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector (requires only VCC levels)
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-definable 64-bit password
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Hardware Features
Program Suspend/Resume & Erase Suspend/
Resume
— Suspends program or erase operations to allow
reading, programming, or erasing in same bank
Hardware Reset (RESET#), Ready/Busy# (RY/
BY#), and Write Protect (WP#) inputs
ACC input
— Accelerates programming time for higher throughput
during system production
Package options
— 80-pin PQFP
— 80-ball Fortified BGA
Publication Number S29CD016_00 Revision A Amendment 4 Issue Date November 5, 2004
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion LLC. Spansion
LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided “as is” without warranty or guarantee of any
kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or
statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.
1 page  
Advance Information
Password Program Command .......................................................... 54
Password Verify Command ............................................................... 54
Password Protection Mode Locking Bit Program Command . 55
Persistent Sector Protection Mode Locking Bit Program Com-
mand ......................................................................................................... 55
SecSi Sector Protection Bit Program Command ........................ 55
PPB Lock Bit Set Command .............................................................. 55
DYB Write Command ........................................................................ 56
Password Unlock Command ............................................................. 56
PPB Program Command ..................................................................... 56
All PPB Erase Command .................................................................... 57
DYB Write .............................................................................................. 57
PPB Lock Bit Set .................................................................................... 57
DYB Status .............................................................................................. 57
PPB Status ............................................................................................... 57
PPB Lock Bit Status .............................................................................. 57
Non-volatile Protection Bit Program And Erase Flow ............. 58
Table 19. Memory Array Command Definitions (x32 Mode)
59
Table 20. Sector Protection Command Definitions (x32
Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 61
DQ7: Data# Polling ............................................................................... 61
Figure 6. Data# Polling Algorithm . . . . . . . . . . . . . . 62
RY/BY#: Ready/Busy# ......................................................................... 63
DQ6: Toggle Bit I .................................................................................. 63
DQ2: Toggle Bit II ................................................................................ 64
Reading Toggle Bits DQ6/DQ2 ........................................................ 64
Figure 7. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . 65
DQ5: Exceeded Timing Limits .......................................................... 66
DQ3: Sector Erase Timer .................................................................. 66
Table 21. Write Operation Status . . . . . . . . . . . . . . . 66
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 67
Figure 8. Maximum Negative Overshoot Waveform . . 67
Figure 9. Maximum Positive Overshoot Waveform . . . 67
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .67
Industrial (I) Devices ...................................................................................................... 67
Extended (E) Devices .................................................................................................... 67
VCC Supply Voltages ...................................................................................................... 67
VIO Supply Voltages ....................................................................................................... 67
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 22. CMOS Compatible . . . . . . . . . . . . . . . . . . . 68
Figure 10. ICC1 Current vs. Time (Showing Active and Auto-
matic Sleep Currents) . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 11. Typical ICC1 vs. Frequency . . . . . . . . . . . . 69
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 12. Test Setup . . . . . . . . . . . . . . . . . . . . . . . 70
Table 23. Test Specifications . . . . . . . . . . . . . . . . . . . 70
Key to Switching Waveforms . . . . . . . . . . . . . . . . 70
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 70
Figure 13. Input Waveforms and Measurement Levels 70
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 14. VCC and VIO Power-up Diagram. . . . . . . . . 71
Table 24. Asynchronous Read Operations . . . . . . . . . . 72
Figure 15. Conventional Read Operations Timings . . . 72
Table 25. Burst Mode Read . . . . . . . . . . . . . . . . . . . . 73
Figure 16. Burst Mode Read (x32 Mode) . . . . . . . . . . 74
Figure 17. Asynchronous Command Write Timing . . . . 75
Figure 18. Synchronous Command Write/Read Timing 75
Table 26. Hardware Reset (RESET#) . . . . . . . . . . . . . 76
Figure 19. RESET# Timings . . . . . . . . . . . . . . . . . . . 76
Figure 20. WP# Timing . . . . . . . . . . . . . . . . . . . . . . 77
Table 27. Erase/Program Operations . . . . . . . . . . . . . 78
Figure 21. Program Operation Timings . . . . . . . . . . . 79
Figure 22. Chip/Sector Erase Operation Timings. . . . . 80
Figure 23. Back-to-back Cycle Timings . . . . . . . . . . . 80
Figure 24. Data# Polling Timings
(During Embedded Algorithms) . . . . . . . . . . . . . . . . 81
Figure 25. Toggle Bit Timings
(During Embedded Algorithms) . . . . . . . . . . . . . . . . 81
Figure 26. DQ2 vs. DQ6 for Erase/Erase Suspend Operations
82
Figure 27. Synchronous Data Polling Timing/Toggle Bit Tim-
ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 28. Sector Protect/Unprotect Timing Diagram . 83
Table 28. Alternate CE# Controlled Erase/Program Opera-
tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 29. Alternate CE# Controlled Write Operation Tim-
ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 29. Erase and Programming Performance . . . . . 86
Table 30. PQFP and Fortified BGA Pin Capacitance . . . . 86
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 87
PRQ080–80-Lead Plastic Quad Flat Package 87
LAA080–80-ball Fortified Ball Grid Array (13 x 11
mm) 88
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 89
November 5, 2004 S29CD016_00_A4
S29CD016G
5
5 Page 
Advance Information
Pin Configuration
A0–A18
DQ0–DQ31
CE#
OE#
WE#
VSS
NC
RY/BY#
CLK
ADV#
IND/WAIT#
WP#
ACC
VIO (VCCQ)
VCC
RESET#
MCH
= 19-bit address bus for 16 Mb device. A9 supports 12
V autoselect inputs.
= 32-bit data inputs/outputs/float
= Chip Enable Input. This signal is asynchronous
relative to CLK for the burst mode.
= Output Enable Input. This signal is asynchronous
relative to CLK for the burst mode.
= Write enable. This signal is asynchronous relative to
CLK for the burst mode.
= Device ground
= Pin not connected internally
= Ready/Busy output and open drain. When RY/BY# =
VIH, the device is ready to accept read operations
and commands. When RY/BY# = VOL, the device is
either executing an embedded algorithm or the
device is executing a hardware reset operation (A
pull-up resistor is required.).
= Clock Input that can be tied to the system or
microprocessor clock and provides the fundamental
timing and internal operating frequency.
= Load Burst Address input. Indicates that the valid
address is present on the address inputs.
= End of burst indicator for finite bursts only. IND/
WAIT# is low when the last word in the burst
sequence is at the data outputs. Otherwise the IND/
WAIT# is high when CE# is low.
= Write Protect input. When WP# = VOL, the two
outermost bootblock sector in the 75% bank are
write protected regardless of other sector protection
configurations.
= Acceleration input. When taken to 12 V, program and
erase operations are accelerated. When not used for
acceleration, ACC = VSS or VCC.
= Output Buffer Power Supply (1.65 V to 2.75 V, 3.6 V
tolerant)
= Chip Power Supply (2.5 V to 2.75 V)
= Hardware reset input
= Must Connect High (to VCC)
November 5, 2004 S29CD016_00_A4
S29CD016G
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S29CD016G.PDF ] | |
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