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PDF VSP2230 Data sheet ( Hoja de datos )
| Número de pieza | VSP2230 | |
| Descripción | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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VSP2230
CCD SIGNAL PROCESSOR
FOR DIGITAL CAMERAS
SLAS319 – MAY 2001
FEATURES
D CCD Signal Processing
– Correlated Double Sampling (CDS)
– Programmable Black Level Clamping
D Programmable Gain Amplifier (PGA)
– –6-dB to 42-dB Gain Ranging
D 10-Bit Digital Data Output
– Up to 36-MHz Conversion Rate
– No Missing Codes
D 76-dB Signal-to-Noise Ratio
D Portable Operation
– Low Voltage: 2.7 V to 3.6 V
– Low Power: 120 mW (typ) at 3.0 V
– Standby Mode: 6 mW
DESCRIPTION
The VSP2230 is a complete mixed-signal processing IC
for digital cameras that provides signal conditioning and
analog-to-digital conversion for the output of a CCD
array. The primary CCD channel provides correlated
double sampling (CDS) to extract the video information
from the pixels, a –6-dB to 42-dB gain with digital control
for varying illumination conditions, and black level
clamping for an accurate black level reference.
Input signal clamping and offset correction of the input
CDS is also performed. The stable gain control is linear
in dB. Additionally, the black level is quickly recovered
after gain change.
The VSP2230Y is pin-to-pin compatible with the
VSP2260Y (10 bit, 20 MHz) one-chip product.
The VSP2230Y is available in a 48-pin LQFP package
and operates from a single 3-V/3.3-V supply.
VSP2230 block diagram
CLPDM SHP SHD
SLOAD SCLK SDATA
RESET
ADCCK DRVDD VCC
CCDIN
Input
Clamp
Serial Interface
Correlated
Double
Sampling (CDS)
Programmable
Gain Amplifier –6 to 42 dB
(PGA)
Timing Control
Analog-to-Digital
Converter
Output
Latch
10-Bit
Digital
Output
B(0–9)
CCD
Output
Signal
Preblanking
Optical Black (OB)
Level Clamping
Reference Voltage Generator
PBLK
COB CPLOB BYPP2 BYP BYPM REFN CM REFP DRVGND
GNDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
www.ti.com
1
1 page  
VSP2230
SLAS319 – MAY 2001
correlated double sampler (CDS) (continued)
The active polarity of SHP/SHD (active high or active low) can be chosen through the serial interface, refer to
serial interface for details. The default value of SHP/SHD is active low. However, right after power on, this value
is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the
default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the
polarity of active low (default value).
input clamp and dummy pixel clamp
The buffered CCD output is capacitively coupled to the VSP2230. The purpose of the input clamp is to restore
the dc component of the input signal that was lost with the ac-coupling and establish the desired dc bias point
for the CDS. Figure 1 shows the simplified block diagram of the input clamp. The input level is clamped to the
internal reference voltage REFN (1.25 V) during the dummy pixel interval. More specifically, when both CLPDM
and SHP are active, then the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM
pulse are not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping
takes place during black pixels. In this case, both CPLDM pin (actives as same timing as CLPOB) and SHP
become active during the optical black pixel interval, then the dummy clamp function becomes active.
The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface,
refer to serial interface for details. The default value of CLPDM and SHP is active low. However, right after power
on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface,
or reset to the default value by the RESET pin. The description and timing diagrams in this data sheet are all
based on the polarity of active low (default value).
high performance analog-to-digital converter (ADC)
The analog-to-digital converter (ADC) utilizes a fully differential and pipelined architecture. This ADC is well
suited for low voltage operation, low power consumption requirement, and high-speed applications. It assures
10-bit resolution of the output data with no missing code. The VSP2230 includes the reference voltage generator
for the ADC. REFP (positive reference, pin 38), REFN (negative reference, pin 39), and CM (common-mode
voltage, pin 37) should be bypassed to the ground with a 0.1-µF ceramic capacitor. Do not use this voltage
anywhere else in the system because it affects the stability of these reference levels, and then causes ADC
performance degradation. These are analog output pins, so do not apply voltage from the outside.
programmable gain amplifier (PGA)
Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of –6 dB to 42 dB, which
is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and it can be settle through the serial
interface, refer to the serial interface section for details. The default value of the gain control code is 128 (PGA
gain = 0 dB). However, right after power on, this value is unknown. For this reason, it must be set to the
appropriate value by using the serial interface, or reset to the default value by the RESET pin.
www.ti.com
5
5 Page 
VSP2230
SLAS319 – MAY 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage (VCC, DRVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Supply voltage differences (among VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Ground voltage differences (among GNDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 5.3 V
Digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.3 V
Analog input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Operating temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR Reflow, Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
electrical characteristics, all specifications at TA = 25°C, VCC = DRVDD = 3 V, conversion rate
f(ADCCK) = 36 MHz, no load unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Resolution
10 Bits
Max conversion rate
36 MHz
Digital inputs
Logic family
TTL
VIT–
VIT+
IIH
IIL
Low-to-high threshold voltage
High-to-low threshold voltage
High-level input current
Low-level input current
ADCCK clock duty cycle
VIN = 3 V
VIN = 0 V
1.9 V
0.9 V
±20
±20 µA
50%
Input capacitance
5 pF
Max input voltage
–0.3 5.3 V
Digital inputs
Logic family
CMOS
Logic coding
Straight
binary
VOH High-level output voltage
VOL Low-level output voltage
IOH = –2 mA
IOL = 2 mA
J[1:0] = 00
2.4
V
0.4
0 ns
Additional output data delay
J[1:0] = 01
J[1:0] = 10
5 ns
10 ns
J[1:0] = 11
13 ns
reference
PARAMETER
Positive reference voltage
Negative reference voltage
TEST CONDITIONS
MIN TYP MAX UNIT
1.75 V
1.25 V
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11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet VSP2230.PDF ] | |
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