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PDF ST2202 Data sheet ( Hoja de datos )
| Número de pieza | ST2202 | |
| Descripción | 8 BIT Integrated Microcontroller with 256K Bytes ROM | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST2202 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ST
Sitronix
ST2202
PRELIMINARY
8 BIT Integrated Microcontroller with 256K Bytes ROM
Notice: This is not a final specification. Some parameters are subject to change.
1. FEATURES
Totally static 8-bit CPU
ROM: 256K x 8-bit
RAM: 4K x 8-bit
Stack: Up to 128-level deep
Operation voltage: 2.4V ~ 5.5V
Operation frequency:
– [email protected](Min.)
– [email protected](Min.)
Low Voltage Detector (LVD)
Memory interface to ROM, RAM, Flash
Memory configuration
– Three kinds of bank for program, data and interrupts
– 12-bit bank register supports up to 44M bytes
– 6 programmable chip-selects with 4 modes
– Maximum single device of 16M bytes at CS5
General-Purpose I/O (GPIO) ports
– 48 multiplexed CMOS bidirectional bit programmable
I/Os
– Hardware de-bounce option for Port-A
– Bit programmable pull-up for input pins
– Bit programmable pull-up/down and open-drain/CMOS
for Port-C
Programmable Watchdog Timer (WDT)
Timer/Counter
– Two 8-bit timer, one can be a 16-bit event counter
– One 8-bit Base timer with 5 coexistent interrupt time
settings
Three clocking outputs
– Clock sources including Timer0/1, baud rate generator
11 prioritized interrupts with dedicated exception
vectors
– External interrupt (edge triggered)
– TIMER0 interrupt
– TIMER1 interrupt
– BASE timer interrupt
– PORTA interrupt (transition triggered)
– DAC reload interrupt
– LCD frame interrupt
– SPI interrupts (x2)
– UART interrupts (x2)
Dual clock sources with warm-up timer
– Low frequency crystal oscillator (OSCX)
····················································32768 Hz
– RC oscillator (OSC) ······························· 500K ~ 4M Hz
– High frequency crystal/resonator oscillator
(Bonding option)······ 455K~4M Hz
Direct Memory Access (DMA)
– Block-to-Block transfer
– Block to Single port
LCD Controller (LCDC)
– Software programmable screen size up to 240X120
(including 160x160, 160x80, etc.)
– Support 1-, 4-bit LCD data bus
– Share system memory with display memory
– Unique internal bus for memory sharing with no loss of
the CPU time
– Diverse functions including virtual screen , panning ,
scrolling , contrast control and alternating signal
generator
– Support software 16 gray levels
Universal Asynchronous Receiver/Transmitter (UART)
– Full-duplex operation
– Baud rate generator with one digital PLL
– Standard baud rates of 600 bps to 115.2 kbps
– Direct glueless support of IrDA physical layer protocol
– Two sets of I/Os (TX,RX) for two independent devices
Serial Peripheral Interface (SPI)
– Master and slave modes
– 5 serial signals including enable and data-ready
– One stage buffer for transmitter and receiver for
continuous data exchange
– Programmable data length from 7-bit to 16-bit
Programmable Sound Generator (PSG)
– Two channels with three playing modes
– Tone/noise generator
– 16-level volume control
– 8-bit PWM DAC for speech/voice
– Two dedicated outputs for directly driving and large
current
Three power down modes
– WAI0 mode
– WAI1 mode
– STP mode
Ver 2.0a
1/65
2003-May-05
1 page  
Sitronix
4. PAD DIAGRAM
ST2202
Ver 2.0a
5/65
2003-May-05
5 Page 
Sitronix
7.4 RAM
Internal static RAM can be divided into 3 parts in function. First
is the zero page memory, second is for stack, and third can be
used as LCD frame buffer or for general purpose.
Zero Page Data RAM ($0080~$00FF)
Total 128 bytes of data RAM in zero page is very useful for
programmers. They provide short instruction codes and cycles.
Use zero page addressing mode on the variables in this area
usually speeds up the overall performance.
Stack RAM ($0100~$01FF)
The ST2202 has 256 bytes stack from $0100 to $01FF. It
provides a maximum of 128 levels for subroutines. By setting
ST2202
stack pointer carefully, stack memory can also be used as data
memory.
User Memory and LCD Frame Buffer
($0200~$0FFF)
The ST2202 shares memory for both user memory and LCD
frame buffer. The range of LCD frame buffer will be fixed after
initialization of LCD control registers. Memory beyond is user
memory. Read and write operations can be applied to LCD
frame buffer to maintain display content, and almost none of
the CPU time is affected. This is contributed by one special
memory transfer technique of display data from LCD frame
buffer to the LCD controller.
Ver 2.0a
11/65
2003-May-05
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST2202.PDF ] | |
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