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PDF MC33091A Data sheet ( Hoja de datos )

Número de pieza MC33091A
Descripción HIGH-SIDE TMOS DRIVER
Fabricantes Motorola Semiconductors 
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High-Side TMOS Driver
The MC33091A is a High–Side TMOS Driver designed for use in harsh
automotive switching applications requiring the capability of handling high
voltages attributed to load and field dump transients, as well as reverse and
double battery conditions. Few external components are required to drive a
wide variety of N–Channel TMOS devices. The MC33091A, driving an
appropriate TMOS device, offers economical system solutions for high–side
switching large currents. The MC33091A has CMOS compatible input
control, charge pump to drive the TMOS power transistor, basic fault
detection circuit, VDS monitoring circuit used to detect a shorted TMOS load,
and overcurrent protection timer with associated current squaring circuitry.
Short circuit protection is made possible by having a unique VDS voltage
to current converter drive an externally programmable integrator circuit. This
circuit affords fast detection of a shorted load while allowing difficult loads,
such as lamps having high in–rush currents, additional time to turn on.
The Fault output is comprised of an open collector NPN transistor
requiring a single pull–up resistor for operation. A fault is reported whenever
the MOSFET on–current exceeds an externally programmed set level.
The MC33091A is available in the plastic 8–Pin DIP package as well as
the plastic 8–Pin surface mount package.
Designed for Automotive High–Side Driver Applications
Works with a Wide Variety of N–Channel Power MOSFETs
Drives Inductive Loads with No External Clamp Circuitry Required
CMOS Logic Compatible Input Control
On–Board Charge Pump with No External Components Required
Shorted Load Detection and Protection
Forward Overvoltage and Reverse Battery Protection
Load and Field Dump Protection
Extended Operating Temperature Range
Fault Output to Report a MOSFET Overcurrent Condition
MC33091A
HIGH–SIDE
TMOS DRIVER
SEMICONDUCTOR
TECHNICAL DATA
8
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
MC33091A
Input
7+
Simplified Block Diagram
RX
2 DRN
Overvoltage
Shutdown
RS
CS 5 VCC
Charge
Pump
+VS
Current
Squaring
Circuit
ISQ
Fault
6
QS +
QR
+
+
Gate
4
SRC
1
Load
3 Gnd
8 VT
RT CT
This device contains 54 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
PIN CONNECTIONS
SRC 1
DRN 2
Gnd 3
Gate 4
8 VT
7 Input
6 Fault
5 VCC
(Top View)
ORDERING INFORMATION
Device
Operating
Temperature Range Package
MC33091AD
SO–8
MC33091AP TA = – 40° to +125°C Plastic DIP
© Motorola, Inc. 1996
Rev 0
1

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MC33091A pdf
MC33091A
Figure 10. Timer Upper Threshold Voltage
versus Temperature
4.64
VCC = 7.0 V
4.62
4.60
VCC = 14 V
4.58
4.56
VCC = 28 V
4.54
Vin = 5.0 V
VTH = Increasing VT
causing Gate turn–off
4.52
4.50
–50
0 50 100
TA, AMBIENT TEMPERATUE (°C)
150
Figure 11. Timer Upper Threshold Voltage
versus Supply Voltage
4.64
4.62
4.60
4.58
Vin = 5.0 V
4.56 VTH = Increasing VT
causing Gate turn–off
4.54
TA = –40°C
TA = 25°C
4.52
4.50
6.0
TA = 125°C
12 18 24
VCC, SUPPLY VOLTAGE (V)
30
Figure 12. Timer Lower Threshold Voltage
versus Temperature
1.10
1.05 7.0 V VCC 28 V
Vin = 5.0 V
1.00 VTL = Decreasing VT
causing Gate turn–on
0.95
0.90
0.85
0.80
0.75
–50
0 50 100
TA, AMBIENT TEMPERATUE (°C)
150
Figure 13. Timer Lower Threshold Voltage
versus Supply Voltage
1.2
1.1 TA = –40°C
1.0
0.9 TA = 25°C
0.8
0.7 TA = 125°C
0.6
0.5
6.0
12
Vin = 5.0 V
VTL = Decreasing VT
causing Gate turn–on
18 24
VCC, SUPPLY VOLTAGE (V)
30
30
25
20
15
10
5.0
0
–5.0
2.0
Figure 14. Gate Voltage versus
Input Control Voltage
VCC = 14 V
TA = 25°C
2.2 2.4 2.6 2.8
Vin, INPUT CONTROL VOLTAGE (V)
3.0
Figure 15. Gate Voltage versus
Supply Voltage
45
40
–40°C TA 125°C
Vin = 5.0 V (Gate “on”)
IG 5.0 µA
35
30
25
20
15
6.0
12 18 24
VCC, SUPPLY VOLTAGE (V)
30
MOTOROLA ANALOG IC DEVICE DATA
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MC33091A arduino
MC33091A
The data sheet for the particular TMOS device being used
will normally reveal the current value, IDS(max), to be
expected under a dead short condition. TMOS data sheets
normally depict graphs of drain current versus drain to source
voltage for various gate to source voltages from which the
drain current at 7.0 V VGS, IDS(max), can reasonably be
approximated. Using this information, the peak TMOS power
dissipation under a dead short condition is approximated
to be:
PD(peak) = VS(max)IDS(max)
(8)
The average power is equal to the peak power dissipation
multiplied by the duty cycle (DC):
PD(avg) = PD(peak)DC
(9)
As long as the average power, in Equation 9, is less than
the maximum power dissipation of the TMOS device under
normal conditions, the short circuit protection scheme of the
MC33091A will adequately protect the TMOS device. The
duty cycle at which the MC33091A controls the gate can be
determined by using Figure 30.
Figure 30. MC33091A Duty Cycle
versus VDS / VDS(min)
10
VTH = 4.6 V
VTL = 0.95 V
8.0 β = VDS/VDS(min)
6.0
DC = 1
4.0
1
+
In
In(VTL/VTH)
(VTH – β2 VTH)
(VTL – β2 VTH)
2.0
0
2.0 4.0 6.0 8.0 10 12
VDS/VDS(min)
As previously discussed, ISQ is externally dependant on
the sensed VDS voltage developed across the TMOS device
and RX in accordance with Equations 1 and 2. At the onset of
an overload condition, the voltage across CT will be less than
the VTH threshold voltage of the upper comparator with the
TMOS device in an “on” state. ISQ current will increase
dramatically and the timing capacitor CT charges toward VTH.
When the voltage on CT reaches the VTH threshold voltage of
the upper comparator, the upper comparator output goes
high setting the latch output (Q) high, turning on the open
collector NPN transistor and pulling the Fault output low. At
the same time, ISQ is switched off, allowing CT to discharge
through resistor RT to VTL, at which time the TMOS device is
again switched on. This action is repeated so long as the
overload condition exists. The VTL and VTH thresholds are
internally set to approximately 0.95 V and 4.6 V respectively.
The charge time (tc) of CT can be shown as:
tc = –RTCT ln[1–(VTH–VTL)/(ISQRT–VTL)] (10)
The discharge time (td) of CT can be shown as:
td = –RTCT ln(VTL/VTH)
(11)
The duty cycle is defined as charge time divided by the
charge plus discharge time and represented by:
DC = tc/(tc+td)
(12)
Substituting Equations 10 and 11 into 12:
DC = 1/1+ln(VTL/VTH)/ln{(VTH–β2VTH)/(VTL–β2VTH)} (13)
where: β = VDS/VDS(min)
Notice the duty cycle is dependent only on the ratio of the
drain to source voltage, VDS, of the TMOS device to the
minimum drain to source voltage, VDS(min), allowing
uninterrupted continuous TMOS operation as calculated in
Equation 5. A graph of Equation 13 is shown in Figure 30 and
is valid for any ratio of VDS to VDS(min). Knowing this ratio, the
duty cycle can be determined by using Figure 30 or Equation
13 and knowing the duty cycle, the average power
dissipation can be calculated by using Equation 9.
If the TMOS device experiences a hard load short to
ground a minimum duty cycle will be experienced which can
be calculated. When this condition exists, the TMOS device
experiences a VDS voltage of VS which is sensed by the
MC33091A. The MC33091A very rapidly charges the timing
capacitor CT to VTH shutting down the TMOS device. This
condition produces the minimum duty cycle for the specific
system conditions. The minimum duty cycle can be
calculated for any valid VS voltage by substituting the value of
VS used for VDS in Equation 13 and solving for the duty cycle.
Knowing the duty cycle and peak power allows
determination of the average power as was pointed out in
Equation 9. TMOS data sheets specify the maximum
allowable junction temperature and thermal resistance,
junction–to–case, at which the device may be operated.
Knowing the average power and the device thermal
information, proper heatsinking of the TMOS device can
be determined.
The duty cycle graph (Figure 30) reveals lower values of
VDS(min) produce shorter duty cycles, for given VDS voltages.
The minimum duty cycle, being limited to the case where
VDS = VS, increases as higher values of VS are used.
MOTOROLA ANALOG IC DEVICE DATA
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