PDF VT8601 Data sheet ( Hoja de datos )

Número de pieza	VT8601
Descripción	Slot-1 / Socket-370 PCI North Bridge
Fabricantes	Via
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ZHFRQQHFW 97 $SROOR3UR0HGLD 0+] 6LQJOH&KLS6ORW6RFNHW3&,1RUWK%ULGJH :LWK,QWHJUDWHG$3''UDSKLFV$FFHOHUDWRU DQG$GYDQFHG0HPRU\&RQWUROOHU VXSSRUWLQJ3&3&DQG9&06'5$0 IRU'HVNWRS3&6\VWHPV 5HYLVLRQ 6HSWHPEHU 9,$7(&+12/2*,(6,1& 1 page :H &RQQHFW7HFKQRORJLHV ,QF VT8601 Apollo ProMedia VGA Registers....................................................................................................................................................................... 70 Attribute Controller Registers (AR) ...................................................................................................................................................... 70 VGA Status / Enable Registers ............................................................................................................................................................. 70 VGA Sequencer Registers (SR) ............................................................................................................................................................ 71 VGA RAMDAC Registers .................................................................................................................................................................... 71 VGA Graphics Controller Registers (GR)............................................................................................................................................. 72 VGA CRT Controller Registers (CR) .................................................................................................................................................. 73 VGA Extended Registers...................................................................................................................................................... 74 VGA Extended Registers – Non-Indexed I/O Ports.............................................................................................................................. 74 VGA Extended Registers – Sequencer Indexed .................................................................................................................................... 75 VGA Extended Registers – Graphics Controller Indexed ..................................................................................................................... 85 VGA Extended Registers – CRT Controller Indexed............................................................................................................................ 91 VGA Extended Registers – CRTC Shadow ........................................................................................................................................ 105 3D Graphics Engine Registers ........................................................................................................................................... 106 Operational Concept ........................................................................................................................................................................... 106 Drawing............................................................................................................................................................................................... 107 Geometry Primitives............................................................................................................................................................................ 108 Synchronization .................................................................................................................................................................................. 111 Functional Blocks ............................................................................................................................................................................... 111 Bus Interface ....................................................................................................................................................................................... 111 Span Engine......................................................................................................................................................................... 112 Graphics Engine Core ........................................................................................................................................................ 113 Graphics Engine Organization ............................................................................................................................................................ 116 Setup Engine Registers ....................................................................................................................................................................... 117 Vertex Registers .................................................................................................................................................................................. 118 Rasterization Engine Registers............................................................................................................................................................ 119 Pixel Engine Registers ........................................................................................................................................................................ 126 Texture Engine Registers .................................................................................................................................................................... 132 Memory Interface Registers ................................................................................................................................................................ 134 Data Port Area..................................................................................................................................................................................... 134 FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 135 SYSTEM CONFIGURATION ......................................................................................................................................................... 135 DFP Interface Configuration............................................................................................................................................. 135 GRAPHICS CONTROLLER POWER MANAGEMENT ................................................................................................................... 136 Power Management States................................................................................................................................................. 136 Power Management Clock Control................................................................................................................................... 136 Power Management Registers ........................................................................................................................................... 136 ELECTRICAL SPECIFICATIONS............................................................................................................................................. 137 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 137 DC CHARACTERISTICS.............................................................................................................................................................. 137 AC TIMING SPECIFICATIONS .................................................................................................................................................... 137 MECHANICAL SPECIFICATIONS ........................................................................................................................................... 138 Revision 1.3 September 8, 1999 -iii- Table of Contents 5 Page :H &RQQHFW7HFKQRORJLHV ,QF VT8601 Apollo ProMedia • DVD − Hardware-Assisted MPEG-2 Architecture for DVD with AC-3 − Simultaneous motion compensation and front-end processing (parsing, decryption and decode) − Supports full DVD 1.0, VCD 2.0 and CD-Karaoke − Microsoft DirectShow 3.0 native support, backward compatible to MCI − No additional frame buffer requirements − Sub-picture hardware eliminates Run-Length-Decoder and Alpha Blending overhead − Dynamic frame and field de-interlace filtering for high quality playback on VGA monitors (Bob and Weave) − Tamper-proof software CSS implementation − Freeze, Fast-Forward, Slow Motion, Reverse − Pan-and-Scan support for 16:9 sequence • Video Processor − On-chip Color Space Converter (CSC) − Anti-tearing via two frame buffer based capture surfaces − Minifier for video stream compression and filtering − Horizontal/vertical interpolation with edge recovery − Dual frame buffer apertures for independent memory access for graphics and video − YUV 4:2:2/4:1:1/4:2:0 and RGB formats − Video Module Interface (VMI) to MPEG and video decoder − Vertical Blank Interval for Intercast™ − Overlay differing video and graphic color depths − Minifier Video Module Interface (VMI) to MPEG and video decode − Display two simultaneous video streams from both internal AGP and VMI − Two scalers and Color Space Converters (CSC) for independent windows • Flat Panel Interface − 85MHz Flat Panel interface supports 1024x768 panels − Support for TFT, STN & DSTN panel technologies − Allows external LVDS or TMDS transmitter for advanced panel interfaces • Power Management Support − Dynamic power down of SDRAM (CKE) − Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus − PCI and AGP bus clock run and clock generator control − VTT suspend power plane preserves memory data − Suspend-to-DRAM and Self-Refresh operation − EDO self-refresh and SDRAM self-refresh power down − 8 bytes of BIOS scratch registers − Low-leakage I/O pads • Testability − Build-in NAND-tree pin scan test capability Revision 1.3 September 8, 1999 -5- Features 11 Page

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