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PDF ST10F163 Data sheet ( Hoja de datos )
| Número de pieza | ST10F163 | |
| Descripción | 16-BIT MCU WITH 128K BYTE FLASH MEMORY | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST10F163
16-BIT MCU WITH 128KBYTE FLASH MEMORY
s HIGH PERFORMANCE CPU
– HIGH PERFORMANCE 16-BIT CPU WITH
4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLE TIME @ 25MHz CPU
CLOCK
– 400ns MULTIPLICATION (16 × 16 BITS)
– 800ns DIVISION (32 / 16 BIT)
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
s MEMORY ORGANIZATION
– UP TO 16 MBYTES LINEAR ADDRESS SPACE
FOR CODE AND DATA (1MBYTE WITH SSP
USED)
– 1 KBYTES ON-CHIP RAM
– 128 KBYTES ON-CHIP FLASH MEMORY
– 4 INDEPENDENTLY ERASABLE BANKS OF
FLASH
s FAST AND FLEXIBLE BUS
– PROGRAMMABLE EBC
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD AND HOLD-ACKNOWLEDGE BUS ARBI-
TRATION SUPPORT
s ON-CHIP BOOTSTRAP LOADER
s FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
s INTERRUPT
– 8-CHANNEL INTERRUPT-DRIVEN SINGLE-CY-
CLE DATA TRANSFER FACILITIES VIA PERIPH-
ERAL EVENT CONTROLLER (PEC)
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM
WITH 20 SOURCES, SAMPLE-RATE DOWN TO
40ns
s TIMERS
– TWO GENERAL PURPOSE TIMER UNITS WITH 5
TIME RS
s CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT
PQFP100 (14 x 14 mm)
(Plastic Quad Flat Pack)
s UP TO 77 GENERAL PURPOSE I/O LINES
s IDLE AND POWER DOWN MODES
s SERIAL CHANNELS
– SYNCHRONOUS/ASYNCHRONOUS
– HIGH-SPEEDSYNCHRONOUS SERIAL PORTSSP
s DEVELOPMENT SUPPORT
– C-COMPILERS, MACRO-ASSEMBLER PACKAG-
ES, EMULATORS, EVALUATION BOARDS,
HLL-DEBUGGERS, SIMULATORS, LOGIC ANA-
LYZER DISASSEMBLERS, PROGRAMMING
BOARDS
s PACKAGE
– 100-PIN THIN QUAD FLAT PACK (TQFP)
CPU
PEC
Interrupt Controller
BRG
P.6 P.5
BRG
P.3
P.2
April 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/58
1 page  
II - PIN DATA
Figure 2 : TQFP pin configuration (top view)
ST10F163
P5.13/T5IN
P5.14/T4EUD
P5.15/T2EUD
VSS
XTAL1
XTAL2
VDD
P3.0
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8
P3.9
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 66
11 65
12
13
ST10F163
64
63
14 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
VSS
VDD
P1H.1/A9
P1H.0/A8
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
5/58
5 Page 
ST10F163
V.1 - Programming/erasing with ST Embedded
Algorithm Kernel
In order to secure flash programming and erasing
operations, and also to simplify the software
development for programming and erasing the
Flash, the ST10F163 Flash is programmed or
erased by executing a specific sequence of
instructions (called ‘Unlock Sequence’) with com-
mand and parameters loaded into GPRs. The
Unlock Sequence’ invokes embedded kernel rou-
tines that checks the validity of the parameters
provided by the user, and decodes the command
(programming or erasing) and executes it.
When performing a programming command, the
Embedded Algorithm Kernel automatically times
the program pulse widths (taking in account the
CPU period provided as a parameter by the user)
and verifies proper cell programming.
When performing an erasing command, the
Embedded Algorithm Kernel automatically
pre-programs the bank to be erased if it is not
already programmed. During erase, the Embed-
ded Algorithm Kernel automatically times the
erase pulse widths (taking in account the CPU
period provided as a parameter by the user) and
verifies proper cell erasing.
To start a program/erase operation, the user’s
application must perform an ‘Unlock Sequence’ to
trigger the flash ST Embedded Algorithms Kernel
(STEAK). Before using STEAK, proper parame-
ters must be assigned through the R0-R4 regis-
ters. The R0 register is the command register. The
other registers handle the address and data to be
programmed or sector to be erased. Table 3
defines the command sequence. A definition of
the codes used in Table 3 is given in Table 4.
Table 3 : Command -parameters definition
COMMAND
R0 R1
R2
R3
Single word programming
Double Word programming
Block programming
Sector Erasing
Read Status
55Ash
DD4sh
AA5sh
EEEEh
7777h
AddOff
AddOff
BegAddOff
5555h
nu
W
DWL
EndAddOff
Bnk
nu
nu
DWH
SourceAddr
Bnk
nu
Note The read status for registers R1 to R3 is not used except for the return values, refer to “Return values” on page 13
Table 4 : Code definition
R4
2TCL
2TCL
2TCL
2TCL
2TCL
Abbreviation
s
AddOff
W
DWL,DWH
BegAddOff
EndAddOff
SourceAdd
Bnk
2TCL
Definition
Segment of the target flash memory cell
Segment Offset of the target flash memory cell which must be even an value (word-aligned address).
Data (word) to be written in flash.
Data (double word, DHL = low word, DWH = high word to be written in Flash,
Segment Offset of the FIRST target flash memory word to be written in a multiple programming com-
mand. This value must be even (word-aligned address)
Segment Offset of the LAST Target Flash Memory word to be written in a Multiple programming
command.
Must be even value (word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <=
D < 16384 (ie. up to one page (16 KBytes) can be written in the flash with one multi-word program-
ming command).
Start address for the source data (block) to be programmed. This address uses implicitly the data
paging mechanism of the CPU. SourceAdd value must respect the rules:
- SourceAdd + (EndAddOff - BegAddOff) < 16384.
- Page 0 and 1 can NOT be used for source data if SYSCON bit ROMS1 = ‘1’
Note: source data can be located in flash (In pages 0, 1, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = ‘0’, or in
pages 4, 5, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = ‘1’.
Number of the Bank to be erased. Note that for security, R2 and R3 must hold the same value.
CPU clock period in nseconds (e.g. R4 = 40d means CPU frequency is 25MHz).
11/58
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST10F163.PDF ] | |
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