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PDF SP6121 Data sheet ( Hoja de datos )
| Número de pieza | SP6121 | |
| Descripción | Low Voltage / Synchronous Step Down PWM Controller Ideal for 2A to 10A / Small Footprint / DC-DC Power Converters | |
| Fabricantes | Sipex | |
| Logotipo |  |
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® SP6121
Low Voltage, Synchronous Step Down PWM Controller
Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters
FEATURES
■ Optimized for Single Input Voltage - 3V to 5.5V
■ High Efficiency: Greater than 95% possible
■ Accurate, 500kHz Fixed Frequency Operation
VCC 1
GND 2
SP6121
8 PDRV
7 NDRV
■ Fast Transient Response
VFB 3
8 Pin SOIC
6 ISET
■ 500µA, IQ (25µA in Shutdown)
■ Internal, 0.4 V/ms, Soft Start Circuit
COMP 4
5 ISENSE
■ Precision 1% Reference
Now Available in Lead Free Packaging
■ Resistor Programmable Output Voltage
■ Lossless Adjustable Current Limit with
■ High Side RDS(ON) Sensing
APPLICATIONS
■ Supply Bias for
- DSP
■ 0% to 100% Duty Cycle Range
- Microprocessor Core
■ High Side PMOS Switch Negates Need for - I/O & Logic
■ External Charge Pump
■ Output Over Voltage Protection
■ Hiccup Mode Current Limit Protection
■ Video Cards
■ Board Level Supply in
Distributed Power Systems
DESCRIPTION
The SP6121 is a fixed frequency, voltage mode, synchronous PWM controller designed to work
from a single 5V or 3.3V input supply, providing excellent AC and DC regulation for high efficiency
power conversion. The operating frequency is internally set at 500kHz, permitting the use of
small, surface mount inductors and capacitors. Requiring only few external components, the
SP6121 packaged in an 8-pin SOIC, is especially suited for low voltage applications where cost,
small size and high efficiency are critical. With its low voltage capability and inherent 100% duty
cycle operation, the SP6121 allows low dropout operation in the event of a low input supply
voltage condition.
TYPICAL APPLICATION CIRCUIT
RVCC
5
CB
3.3µF
®
VCC PDRV
SP6121
GND U1 NDRV
VFB ISET
RSET
2.3k
Q1
Q2 DS
CIN
47µF
Ceramic 6.3V
3.3V
VIN
1.8µH
L1
COUT
470µF x 2
1.9V 8A
VOUT
R1
5.2k
CP
50pF
COMP
RZ
10k
CZ
3.7nF
ISENSE
R2
10k
Q1 = FAIRCHILD FDS6375
Q2 = FAIRCHILD FDS6690A
DS = STMICROELECTRONICS STPS2L25BU
L1 = PANASONIC ETQ-P6F1R6SFA
COUT = SANYO 4TPB470M
Date: 5/25/04
SP6121 Low Voltage, Synchronous Step Down PWM Controller
1
© Copyright 2004 Sipex Corporation
1 page  
THEORY OF OPERATION: continued
value is selected to match the MOSFET charac-
teristics. When the over-current threshold is
exceeded, the over-current comparator sets the
fault latch and terminates the output pulses. The
controller stops switching and goes through a
hiccup sequence. This prevents excessive power
dissipation in the external power MOSFETs
during an overload condition. An internal delay
circuit prevents that very short and mild over-
load conditions, that could occur during a load
transient, activate the current limit circuit.
A low power sleep mode can be invoked in the
SP6121 by externally forcing the COMP pin
below 0.3V. Quiescent supply current in sleep
mode is typically less than 25µA. An internal
5µA pull-up current at the COMP pin brings the
SP6121 out of shutdown mode.
The SP6121 also includes under-voltage lock-
out and over-voltage protection. Output over-
voltage protection is achieved by turning off the
high side switch, and turning on the low side N-
channel MOSFET full time.
Enable
Low quiescent mode or “Sleep Mode” is initi-
ated by pulling the COMP pin below 0.3V with
an external open-drain or open-collector tran-
sistor. Supply current is reduced to 25µA (typi-
cal) in shutdown. On power-up, assuming that
VCC has exceeded the UVLO start threshold
(2.79V), an internal 5µA pull-up current at the
COMP pin brings the SP6121 out of shutdown
mode and ensures start-up. During normal oper-
ating conditions and in absence of a fault, an
internal clamp prevents the COMP pin from
swinging below 0.6V. This guarantees that dur-
ing mild transient conditions, due either to line
or load variations, the SP6121 does not enter
shutdown unless it is externally activated.
During Sleep Mode, the high side and low side
MOSFETs are turned off and the internal soft
start voltage is held low.
UVLO
Assuming that there is not shutdown condition
present, then the voltage on the VCC pin deter-
mines operation of the SP6121. As VCC rises,
the UVLO block monitors VCC and keeps the
high side and low side MOSFETS off and the
internal SS voltage low until VCC reaches 2.79V.
If no faults are present, the SP6121 will initiate
a soft start when VCC exceeds 2.79V.
Hysteresis (about 100mV) in the UVLO com-
parator provides noise immunity at start-up.
Soft Start
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a timing
capacitor and then using the voltage across this
capacitor to slowly ramp up either the error amp
reference or the error amp output (COMP). The
control loop creates narrow width driver pulses
while the output voltage is low and allows these
pulses to increase to their steady-state duty
cycle as the output voltage increases to its regu-
lated value. As a result of controlling the induc-
tor volt*second product during startup, inrush
current is also controlled.
In the SP6121 the duration of the soft-start is
controlled by an internal timing circuit that
provides a 0.4V/ms slew-rate, which is used
during start-up and over-current to set the hic-
cup time. The SP6121 implements soft-start by
ramping up the error amplifier reference voltage
providing a controlled slew-rate of the output
voltage, thereby preventing overshoot and in-
rush current at power up.
The presence of the output capacitor creates
extra current draw during startup. Simply stated,
dVOUT/dt requires an average sustained current
in the output capacitor and this current must be
considered while calculating peak inrush cur-
rent and over current thresholds. An approxi-
mate expression to determine the excess inrush
current due to the dVOUT/dt of the output capaci-
tor COUT is:
VOUT
ICOUT = COUT*(0.4 V/ms) * 1.25
As Figure 1 shows, the SS voltage controls a
variety of signals. First, provided all the exter-
nal fault conditions are removed, an internal
5µA pull-up at the COMP pin brings the SP6121
out of shutdown mode. The internal timing
circuit is then activated and controls the ramp-
up of the error amp reference voltage. The
COMP pin is pulled to 0.7V by the internal
Date: 5/25/04
SP6121 Low Voltage, Synchronous Step Down PWM Controller
5
© Copyright 2004 Sipex Corporation
5 Page 
APPLICATIONS INFORMATION: Continued
well as provide typical curve of RDS(ON) versus
VGS. For 5V input, use the RDS(ON) specified at
4.5V VGS. At the time of this publication, ven-
dors, such as Fairchild, Siliconix and Interna-
tional Rectifier, have started to specify RDS(ON)
at VGS less than 3V. This has provided necessary
data for designs in which these MOSFETs are
driven with 3.3V and made it possible to use
SP6121 in 3.3V only applications.
Thermal calculation must be conducted to en-
sure the MOSFET can handle the maximum
load current. The junction temperature of the
MOSFET, determined as follows, must stay
below the maximum rating.
TJ (max)
= TA (max)
+
PMOSFET (max)
Rθ JA
,
where;
TA(max) = maximum ambient temperature
PMOSFET(max) = maximum power dissipation of
the MOSFET
RθJA = junction to ambient thermal resistance.
RθJA of the device depends greatly on the board
layout, as well as device package. Significant
thermal improvement can be achieved in the
maximum power dissipation through the proper
design of copper mounting pads on the circuit
board. For example, in a SO-8 package, plac-
ing two 0.04 square inches copper pad di-
rectly under the package, without occupying
additional board space, can increase the maxi-
mum power from approximately 1 to 1.2W.
For DPAK package, enlarging the tap mount-
ing pad to 1 square inches reduces the RθJA
from 96°C/W to 40°C/W.
Schottky Diode Selection
When paralleled with the bottom MOSFET, an
optional Schottky diode can improve efficiency
and reduce noise. Without this Schottky diode,
the body diode of the bottom MOSFET con-
ducts the current during the non-overlap time
when both MOSFETs are turned off. Unfortu-
nately, the body diode has high forward voltage
and reverse recovery problem. The reverse re-
covery of the body diode causes additional
switching noises when the diode turns off. The
Schottky diode alleviates this noise and addi-
tionally improves efficiency thanks to its low
forward voltage. The reverse voltage across the
diode is equal to input voltage, and the diode
must be able to handle the peak current equal to
the maximum load current.
The power dissipation of the Schottky diode is
determined by
PDIODE = 2VFIOUTTNOLFS
where;
TNOL = non-overlap time between PDRV and
NDRV.
VF = forward voltage of the Schottky diode.
COMP
®
R1
C2
C1
SP6121
Figure 4. The RC network connected to the COMP pin
provides a pole and a zero to control loop.
Loop Compensation Design
The goal of loop compensation is to manipulate
loop frequency response such that its gain crosses
over 0db at a slope of -20db/dec. The SP6121
has a trans-conductance error amplifier and re-
quires the compensation network to be con-
nected between the COMP pin and ground, as
shown in Figure 4.
The first step of compensation design is to pick
the loop crossover frequency. High crossover
frequency is desirable for fast transient response,
but often jeopardize the system stability. Cross-
over frequency should be higher than the ESR
zero but less than 1/5 of the switching fre-
quency. The ESR zero is contributed by the ESR
Date: 5/25/04
SP6121 Low Voltage, Synchronous Step Down PWM Controller
11
© Copyright 2004 Sipex Corporation
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet SP6121.PDF ] | |
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