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PDF SCN2681 Data sheet ( Hoja de datos )
| Número de pieza | SCN2681 | |
| Descripción | Dual asynchronous receiver/transmitter DUART | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
SCN2681
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN2681
PIN DESCRIPTION (Continued)
APPLICABLE
SYMBOL
40/44 28 24
TYPE
IP5 X
I
IP6 X
I
VCC
GND
XX
XX
I
I
NAME AND FUNCTION
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
Power Supply: +5V supply input.
Ground
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATING
UNIT
TA
TSTG
Operating ambient temperature range2
Storage temperature range
All voltages with respect to ground3
See Note 4
-65 to +150
-0.5 to +6.0
°C
°C
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150oC maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3 TA = -40°C to +85°C, VCC = +5.0V " 10%
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min Typ Max
UNIT
VIL
VIH
VIH
VIH
VOL
VOH
VOH
IIL
ILL
IX1L
IX1H
IX2L
IX2H
IOC
IOCC
Input low voltage
Input high voltage (except X1/CLK)5
Input high voltage (except X1/CLK)4
Input high voltage (X1/CLK)
Output low voltage
Output high voltage (except o.d. outputs)5
Output high voltage (except o.d. outputs)4
Input leakage current
Data bus 3-stage leakage current
X1/CLK low input current
X1/CLK high input current
X2 low input current
X2 high input current
Open-collector output leakage current
Power supply current
IOL = 2.4mA
IOH = -400µA
IOH = -400µA
VIN = 0 to VCC
VO = 0.4 to VCC
VIN = 0, X2 grounded
VIN = 0, X2 floated
VIN = VCC, X2 grounded
VIN = VCC, X2 floated
VIN = 0, X1/CLK floated
VIN = VCC, X1/CLK floated
VO = 0.4 to VCC
0°C to +70°C version
-40°C to +85°C version
0.8 V
2V
2.5 V
4V
0.4 V
2.4 V
2.9 V
-10 10 µA
-10 -2 10 µA
-4 -1.5 0 mA
-3 0.2 0 mA
-1 3.5 1 mA
0 -30 10 mA
-100 +30
0
µA
0 100 µA
-10 10 µA
150 mA
175 mA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages
of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. TA < 0°C
5. TA > 0°C
1998 Sep 04
5
5 Page 
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN2681
Table 2. Register Bit Formats
BIT 7
BIT 6
MR1A
MR1B
RxRTS
CONTROL
0 = No
1 = Yes
RxINT
SELECT
0 = RxRDY
1 = FFULL
BIT 5
ERROR
MODE*
0 = Char
1 = Block
BIT 4
BIT 3
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BIT 2
PARITY
TYPE
0 = Even
1 = Odd
BIT 1
BIT 0
BITS PER
CHARACTER
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
MR2A
MR2B
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
TxRTS
CONTROL
0 = No
1 = Yes
CTS
ENABLE Tx
0 = No
1 = Yes
NOTE:
*Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
BIT 3
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
BIT 2
BIT 1
STOP BIT LENGTH*
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
BIT 0
C = 1.813
D = 1.875
E = 1.938
F = 2.000
CSRA
CSRB
BIT 7
BIT 6
BIT 5
RECEIVER CLOCK SELECT
See Text
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TRANSMITTER CLOCK SELECT
See Text
NOTE:
* See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
Not used –
should be 0
MISCELLANEOUS COMMANDS
See Text
DISABLE Tx
0 = No
1 = Yes
ENABLE Tx
0 = No
1 = Yes
DISABLE Rx
0 = No
1 = Yes
ENABLE Rx
0 = No
1 = Yes
NOTE:
*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
RECEIVED
BREAK*
0 = No
1 = Yes
FRAMING
ERROR*
0 = No
1 = Yes
PARITY
ERROR*
0 = No
1 = Yes
OVERRUN
ERROR
0 = No
1 = Yes
TxEMT
0 = No
1 = Yes
TxRDY
0 = No
1 = Yes
FFULL
0 = No
1 = Yes
RxRDY
0 = No
1 = Yes
NOTE:
* These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded
when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error
reset command (command 4x) or a receiver reset.
OPCR
BIT 7
OP7
0 = OPR[7]
1 = TxRDYB
BIT 6
OP6
0 = OPR[6]
1 = TxRDYA
BIT 5
OP5
0 = OPR[5]
1 = RxRDY/
FFULLB
BIT 4
OP4
0 = OPR[4]
1 = RxRDY/
FFULLA
BIT 3
BIT 2
OP3
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1x)
11 = RxCB(1x)
OPR
BIT 7
BIT 6
BIT 5
BIT 4
OPR bit 0 1 0 1 0 1 0 1
OP pin 1 0 1 0 1 0 1 0
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.
BIT 3
01
10
BIT 2
01
10
1998 Sep 04
11
BIT 1
BIT 0
OP2
00 = OPR[2]
01 = TxCA(16x)
10 = TxCA(1x)
11 = RxCA(1x)
BIT 1
01
10
BIT 0
01
10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SCN2681.PDF ] | |
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