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74HCT138 の電気的特性と機能

74HCT138のメーカーはPhilipsです、この部品の機能は「3-to-8 line decoder/demultiplexer inverting」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HCT138
部品説明 3-to-8 line decoder/demultiplexer inverting
メーカ Philips
ロゴ Philips ロゴ 




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74HCT138 Datasheet, 74HCT138 PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT138
3-to-8 line decoder/demultiplexer;
inverting
Product specification
File under Integrated Circuits, IC06
September 1993

1 Page





74HCT138 pdf, ピン配列
Philips Semiconductors
3-to-8 line decoder/demultiplexer; inverting
PIN DESCRIPTION
PIN NO.
1, 2, 3
4, 5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
SYMBOL
A0 to A2
E1, E2
E3
GND
Y0 to Y7
VCC
NAME AND FUNCTION
address inputs
enable inputs (active LOW)
enable input (active HIGH)
ground (0 V)
outputs (active LOW)
positive supply voltage
Product specification
74HC/HCT138
Fig.1 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
A0
A1
A2
E1
E2
E3
Y0 15
Y1 14
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
MLB312
Fig.2 Logic symbol.
(a) (b)
Fig.3 IEC logic symbol.
September 1993
3
Fig.4 Functional diagram.


3Pages


74HCT138 電子部品, 半導体
Philips Semiconductors
3-to-8 line decoder/demultiplexer; inverting
Product specification
74HC/HCT138
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To
determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
An
En
E3
UNIT LOAD COEFFICIENT
1.50
1.25
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25 40 to +85
min. typ. max. min. max.
40 to +125
min. max.
UNIT
VCC WAVEFORMS
(V)
tPHL/ tPLH
propagation delay
An to Yn
20 35
44
53 ns 4.5 Fig.6
tPHL/ tPLH
propagation delay
E3 to Yn
18 40
50
60 ns 4.5 Fig.6
tPHL/ tPLH
propagation delay
En to Yn
19 40
50
60 ns 4.5 Fig.7
tTHL/ tTLH
output transition
time
7 15
19
22 ns 4.5 Figs 6 and 7
September 1993
6

6 Page



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