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74HC164 の電気的特性と機能

74HC164のメーカーはFairchildです、この部品の機能は「8-Bit Serial-in/Parallel-out Shift Register」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HC164
部品説明 8-Bit Serial-in/Parallel-out Shift Register
メーカ Fairchild
ロゴ Fairchild ロゴ 




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74HC164 Datasheet, 74HC164 PDF,ピン配置, 機能
September 1983
Revised February 1999
MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low con-
sumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky devices.
This 8-Bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A
LOW at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock
pulse. A high level on one input enables the other input
which will then determine the state of the first flip-flop. Data
at the serial inputs may be changed while the clock is HIGH
or LOW, but only information meeting the setup and hold
time requirements will be entered. Data is serially shifted in
and out of the 8-Bit register during the positive going transi-
tion of the clock pulse. Clear is independent of the clock
and accomplished by a low level at the CLEAR input.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
Features
s Typical operating frequency: 50 MHz
s Typical propagation delay: 19 ns (clock to Q)
s Wide operating supply voltage range: 2–6V
s Low input current: 1 µA maximum
s Low quiescent supply current: 80 µA maximum (74HC
Series)
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC164M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC164MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC164N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC and TSSOP
Inputs
Clear Clock A
L XX
H LX
H H
H L
H X
Outputs
B QA QB
...
XL
L
X QAO QBO
H H QAn
X L QAn
L L QAn
QH
L
QHO
QGn
QGn
QGn
H = HIGH Level (steady state), L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW-to-HIGH level.
QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indi-
cated steady state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent transition of the
clock; indicated a one-bit shift.
Top View
© 1999 Fairchild Semiconductor Corporation DS005315.prf
www.fairchildsemi.com

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74HC164 pdf, ピン配列
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.0V
1.5 to VCC +1.5V
0.5 to VCC +0.5V
±20 mA
±25 mA
±50 mA
65°C to +150°C
600 mW
500 mW
260°C
Min Max Units
Supply Voltage (VCC)
DC Input or Output Voltage
26
V
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
0
40
VCC
+85
V
°C
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C
Units
Typ Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level
Input Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH Minimum HIGH Level
Output Voltage
VIN = VIH or VIL
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VOL Maximum LOW Level
Output Voltage
VIN = VIH or VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VIH or VIL
|IOUT| 20 µA
4.5V 4.2 3.98
6.0V 5.7 5.48
2.0V
4.5V
0
0
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
IIN Maximum Input
Current
VIN = VIH or VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VCC or GND
4.5V 0.2 0.26
6.0V 0.2 0.26
6.0V
±0.1
0.33
0.33
±1.0
0.4
0.4
±1.0
V
V
µA
ICC Maximum Quiescent
VIN = VCC or GND
6.0V
8.0 80
160 µA
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3 www.fairchildsemi.com


3Pages


74HC164 電子部品, 半導体
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
6

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