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82S123 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 82S123
部品説明 256-bit TTL bipolar PROM
メーカ NXP
ロゴ NXP ロゴ 

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82S123 Datasheet, 82S123 PDF,ピン配置, 機能
Philips Semiconductors
256-bit TTL bipolar PROM (32 x 8)
Product specification
82S23/82S123
DESCRIPTION
The 82S23 and 82S123 are field
programmable, which means that
custom patterns are immediately
available by following the Signetics
Generic I fusing procedure. The 82S23
and 82S123 devices are supplied with
all outputs at logical Low. Outputs are
programmed to a logic High level at any
specified address by fusing the Ni-Cr
link matrix.
These devices include on-chip decoding
and 1 Chip Enable input for memory
expansion. They feature either Open
Collector or 3-State outputs for
optimization of word expansion in bused
organizations.
Ordering information can be found on
the following page.
The 82S23 and 82S123 devices are
also processed to military requirements
for operation over the military
temperature range. For specifications
and ordering information, consult the
Signetics Military Data Handbook.
FEATURES
Address access time: 50ns max
Power dissipation: 1.3mW/bit typ
Input loading: –100µA max
On-chip address decoding
One Chip Enable input
Output options:
N82S23: Open Collector
N82S123: 3-State
No separate fusing pins
Unprogrammed outputs are Low level
Fully TTL compatible
APPLICATIONS
Prototyping/volume production
Sequential controllers
Format conversion
Hardwired algorithms
Random logic
Code conversion
PIN CONFIGURATIONS
N Package
O1 1
O2 2
O3 3
O4 4
O5 5
O6 6
O7 7
GND 8
16 VCC
15 CE
14 A4
13 A3
12 A2
11 A1
10 A0
9 O8
A Package
O2 O1 NC VCC CE
3 2 1 20 19
O3 4
18 A4
O4 5
17 A3
NC 6
16 NC
O5 7
15 A2
O6 8
14 A1
9 10 11 12 13
O7 GND NC O8 A0
BLOCK DIAGRAM
A0
ADDRESS
LINES
A4
1:32
DECODER
32 × 8 MATRIX
CE 8 OUTPUT DRIVERS
O1 O2 O3 O4 O5 O6 O7 O8
OUTPUT LINES
November 11, 1986
1
853-0154 86487

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