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74VHC245 の電気的特性と機能

74VHC245のメーカーはFairchild Semiconductorです、この部品の機能は「Octal Bidirectional Transceiver with 3-STATE Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 74VHC245
部品説明 Octal Bidirectional Transceiver with 3-STATE Outputs
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74VHC245 Datasheet, 74VHC245 PDF,ピン配置, 機能
November 1992
Revised March 1999
74VHC245
Octal Bidirectional Transceiver with 3-STATE Outputs
General Description
The VHC245 is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipo-
lar Schottky TTL while maintaining the CMOS low power
dissipation. The VHC245 is intended for bidirectional asyn-
chronous communication between data busses. The direc-
tion of data transmission is determined by the level of the
T/R input. The enable input can be used to disable the
device so that the busses are effectively isolated. All inputs
are equipped with protection circuits against static dis-
charge.
Features
s High Speed: tPD = 4.0 ns (typ) at VCC = 5V
s High Noise Immunity: VNIH = VNIL = 28% VCC (Min)
s Power Down Protection is provided on all inputs
s Low Noise: VOLP = 0.9V (typ)
s Low Power Dissipation:
ICC = 4 µA (Max) @ TA = 25°C
s Pin and Function Compatible with 74HC245
Ordering Code:
Order Number Package Number
Package Description
74VHC245M
M20B
20-Lead Small Outline Integrated Package (SOIC), JEDEC MS-013, 0.300” Wide
74VHC245SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC245N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Description
Pin
Names
OE
T/R
A0–A7
B0–B7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011520.prf
Truth Table
Inputs
Outputs
OE T/R
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X HIGH-Z State
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Any unused bus terminals during HIGH-Z State must be held HIGH or
LOW.
www.fairchildsemi.com

1 Page





74VHC245 pdf, ピン配列
Noise Characteristics
Symbol
Parameter
VOLP
(Note 3)
VOLV
(Note 3)
VIHD
(Note 3)
Quiet Output Maximum
Dynamic VOL
Quiet Output Minimum
Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
VILD
(Note 3)
Maximum LOW Level
Dynamic Input Voltage
Note 3: Parameter guaranteed by design.
VCC
TA = 25°C
Units
(V) Typ Limits
Conditions
5.0 0.9 1.2
V CL = 50 pF
5.0
0.9
1.2
V CL = 50 pF
5.0 3.5 V CL = 50 pF
5.0 1.5 V CL = 50 pF
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = 25°C
TA = −40°C to +85°C
Units
Min Typ Max Min Max
Conditions
tPLH Propagation Delay
tPHL
Time
tPZL 3-STATE Output
tPZH
Enable Time
tPLZ
tPHZ
tOSLH
tOSHL
CIN
3-STATE Output
Disable Time
Output to Output
Skew
Input Capacitance
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
5.8 8.4 1.0 10.0
ns
8.3 11.9 1.0 13.5
CL = 15 pF
CL = 50 pF
4.0 5.5 1.0 6.5
ns
5.5 7.5 1.0 8.5
CL = 15 pF
CL = 50 pF
8.5
13.2
1.0
15.5
ns RL = 1 kCL = 15 pF
11.0 16.7 1.0 19.0
CL = 50 pF
5.8 8.5 1.0 10.0
ns
7.3 10.6 1.0 12.0
CL = 15 pF
CL = 50 pF
11.5 15.8
1.0
18.0
ns RL = 1 kCL = 50 pF
7.0 9.7 1.0 11.0
CL = 50 pF
1.5 1.5 ns (Note 4) CL = 50 pF
1.0 1.0
CL = 50 pF
4 10
10 pF VCC = Open
(T/R, OE)
CI/O Output Capacitance
CPD Power Dissipation
Capacitance
8
21
pF VCC = 5.0V
pF (Note 5)
Note 4: Parameter guaranteed by design. tOSLH = |tPLH max tPLH min|; tOSHL = |tPHL max tPHL min|
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per Bit).
3 www.fairchildsemi.com


3Pages


74VHC245 電子部品, 半導体
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

6 Page



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