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74VHC02N の電気的特性と機能

74VHC02NのメーカーはFairchild Semiconductorです、この部品の機能は「Quad 2-Input NOR Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74VHC02N
部品説明 Quad 2-Input NOR Gate
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74VHC02N Datasheet, 74VHC02N PDF,ピン配置, 機能
December 2007
74VHC02
Quad 2-Input NOR Gate
Features
High Speed: tPD = 3.6ns (Typ.) at VCC = 5V
Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (Min.)
Power down protection is provided on all inputs
Low noise: VOLP = 0.8V (Max.)
Pin and function compatible with 74HC02
General Description
The VHC02 is an advanced high-speed CMOS 2-Input
NOR Gate fabricated with silicon gate CMOS technol-
ogy. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The internal circuit is
composed of 3 stages, including buffer output, which
provide high noise immunity and stable output. An input
protection circuit insures that 0V to 7V can be applied to
the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and
two supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Order Number
Package
Number
Package Description
74VHC02M
74VHC02SJ
74VHC02MTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
www.fairchildsemi.com

1 Page





74VHC02N pdf, ピン配列
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
TSTG
TL
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC VCC / GND Current
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to VCC + 0.5V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Recommended Operating Conditions(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC
VIN
VOUT
TOPR
tr, tf
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
VCC = 3.3V ± 0.3V
VCC = 5.0V ± 0.5V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Rating
2.0V to +5.5V
0V to +5.5V
0V to VCC
–40°C to +85°C
0ns/V 100ns/V
0ns/V 20ns/V
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
3
www.fairchildsemi.com


3Pages


74VHC02N 電子部品, 半導体
Physical Dimensions
8.75
8.50
7.62
14
6.00
A
8
B
4.00
3.80
0.65
5.60
PIN ONE
INDICATOR
1
1.27
(0.33)
7
0.51
0.35
1.70 1.27
LAND PATTERN RECOMMENDATION
0.25 M C B A
1.75 MAX
1.50
1.25
R0.10
R0.10
8°
0°
SEE DETAIL A
0.25
0.10 C
0.10 C
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
X 45°
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE FLASH OR BURRS.
D) LANDPATTERN STANDARD:
0.36
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
6
www.fairchildsemi.com

6 Page



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