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PDF 74VHC02M Data sheet ( Hoja de datos )
| Número de pieza | 74VHC02M | |
| Descripción | Quad 2-Input NOR Gate | |
| Fabricantes | Fairchild Semiconductor | |
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December 2007
74VHC02
Quad 2-Input NOR Gate
Features
■ High Speed: tPD = 3.6ns (Typ.) at VCC = 5V
■ Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (Min.)
■ Power down protection is provided on all inputs
■ Low noise: VOLP = 0.8V (Max.)
■ Pin and function compatible with 74HC02
General Description
The VHC02 is an advanced high-speed CMOS 2-Input
NOR Gate fabricated with silicon gate CMOS technol-
ogy. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The internal circuit is
composed of 3 stages, including buffer output, which
provide high noise immunity and stable output. An input
protection circuit insures that 0V to 7V can be applied to
the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and
two supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Order Number
Package
Number
Package Description
74VHC02M
74VHC02SJ
74VHC02MTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH Propagation Delay
CIN Input Capacitance
CPD Power Dissipation
Capacitance
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
VCC = Open
(3)
TA = 25°C
Min. Typ. Max.
5.6 7.9
8.1 11.4
3.6 5.5
5.1 7.5
4 10
15
TA = –40°C
to +85°C
Min. Max.
1.0 9.5
1.0 13.0
1.0 6.5
1.0 8.5
10
Units
ns
ns
pF
pF
Note:
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per gate).
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VHC02M.PDF ] | |
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