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PDF MC143416PB Data sheet ( Hoja de datos )
| Número de pieza | MC143416PB | |
| Descripción | Dual 16-Bit Linear Codec-Filter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Dual 16-Bit Linear Codec-Filter
The MC143416 Dual 16–Bit Linear Codec–Filter is a single–chip imple-
mentation of the data conversion interface required to design high–speed
modems meeting a wide range of standards such as ITU–T V.34 and PCM
modem. It includes two high performance Analog–to–Digital (A/D) and
Digital–to–Analog (D/A) data converters. The device performs all filtering
operations related to the conditioning and sample rate conversion of signals to
and from the data interface. Output from both codecs (COder/DECoder) is in
16–bit 2s complement format.
The MC143416 includes the necessary logic needed to generate all clocks
(oversampling, intermediate frequency, and baud rate) required to perform the
data processing operations involved in the oversampling conversion of voice
and data signals. Sample rates are fully programmable in the range of 8
kilosamples/second (ks/s) to 16 ks/s, including 8000, 9600, 11025, 12000, and
16000 samples/second. The bandwidth of the MC143416 is 0.425 * Sample
Frequency (FS).
The MC143416 includes two Synchronous Serial Interfaces (SSIs) through
which an external Digital Signal Processor (DSP) can configure and monitor the
operation of the device. Digital sample data is transferred to and from the
codecs through the serial ports. In addition, information can be written and read
to the control and status registers of the device via the serial port, transparent to
the flow of sample data. When used in a high–speed modem application, the
MC143416 provides the analog front end interface required to support modem
and voice features.
MC143416 Features
• Fully–Differential Analog Circuit Design for Lowest Noise
• Two High Performance 16–Bit Sigma–Delta A/D and D/A Converters
• Band–Pass and Low–Pass Filtering for Both Codecs is Performed
On–Chip
• Power Monitor Circuit
• Single 5 V ± 5% Power Supply
• Two Configurable Serial Ports
• On–Chip Precision Reference Voltage
• On–Chip Speaker Driver and Mixer with Programmable Gain — Capable of
Delivering 15 mW of Power into a Small Speaker (32 Ω)
• Bandwidth is 0.425 * FS
• No External Filtering Required Because of Flat Response Over Passband
• Capable of Providing the Analog Front End for Wide Range of Modem
Standards
Order this document
by MC143416/D
MC143416
44 PB SUFFIX
1 TQFP
CASE 824D
ORDERING INFORMATION
MC143416PB TQFP
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
11/97 TN97112000
©MOMoTtoOroRla,OInLc.A1997
MC143416
1
1 page  
ANALOG TRANSMISSION PERFORMANCE
(VDD = 4.75 to 5.25 V, AGND = 0 V, All Analog Signals Referenced to VAG, 0.775 Vrms = 0 dBm into 600 Ω, FSR = 8 kHz,
Measurement Band = 200 to 0.425 * FS, MCLK = 2.048 MHz Synchronous Operation, TA = – 40 to 85°C, Unless Otherwise Noted)
A/D D/A
Dynamic Range
Characteristics
Min Typ Max Min Typ Max Unit
— 78 — — 80 — dB
Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VDD = 5.0 V)
Total Signal to Noise + Distortion
– 3 dBm0
– 10 dBm0
– 20 dBm0
—
—
—
—
– 3.8
75
70
60
—
—
—
—
— 9.0 — dB
— 75 — dB
— 71 —
— 63 —
Idle Channel Noise (dBrn0)
— 12 — — 13 — dBrn0
Frequency Response (Relative to 1.02 kHz @ 0 dBm0) (HB = 0)
60 Hz
300 to 3000 Hz
3400 Hz
4000 Hz
≥ 4600 Hz
—
—
—
—
—
– 20
0.15
– 0.15
– 35
– 70
—
—
—
—
—
— ± 0.15 —
— ± 0.15 —
— – 0.10 —
— – 20 —
— – 32 —
dB
Absolute Delay (1600 Hz) (HB = 0)
— 318 —
— 214 —
µs
Group Delay Referenced to 1600 Hz (HB = 0)
500 to 600 Hz — 96 —
600 to 800 Hz — 46 —
800 to 1000 Hz — 2 —
1000 to 1600 Hz — 0 —
1600 to 2600 Hz — 22 —
2600 to 2800 Hz — 189 —
2800 to 3000 Hz — 290 —
— – 26 —
— – 24 —
— – 20 —
— – 18 —
— 86 —
— 120 —
— 169 —
µs
Crosstalk (Within Channels) of 1020 Hz @ 0 dBm0 from A/D or D/A*
— – 86 —
— – 93 —
dB
* Selectively measured while stimulated with 2667 Hz @ – 50 dBm0.
MOTOROLA
MC143416
5
5 Page 
REGISTER PROGRAMMING
REGISTER PROGRAMMING MODEL
Table 4 is the register map of the MC143416’s control and
status registers. Registers labeled with a 0 suffix are
associated with SSI Port 0, and those with a 1 suffix are
associated with SSI Port 1. For example, register CNTL0_0
is associated with SSI Port 0, and CNTL0_1 is associated
with SSI Port 1.
CONTROL AND STATUS REGISTERS
The MC143416 provides ten 8–bit control/status registers
that are available to use. The MSB of all these registers is
always 0 as a safety feature against desynchronization (ad-
dress/data swap). Each register is doubled to serve one
associated codec, with the exception of register CNTL4,
CNTL5, CNTL6, and CNTL7, which carry global chip con-
trols. These registers are accessible by either SSI port.
In the following paragraphs, the contents of each register
are discussed in detail. In the description of each individual
bit, two parameters are included: access and reset value. Ac-
cess indicates whether the bit is read only, write only, or both;
reset value indicates the value upon reset. All register bits
are static except SWRESET in CNTL4.
CNTL0_0: Power Control Register — Codec 0
ANARSVD0 (R/W, 0): This bit is reserved for future use
and must be kept 0.
ALOOP (R/W, 0): This bit controls the remote loopback
function at the analog/digital interface. Setting this bit to 1 will
force the single bit modulated output from Rx in the codec to
loopback into the single bit input of the D/A. See Figure 2.
DLOOP (R/W, 0): Setting this bit to 1 will force a digital
loopback in the codec. This occurs at a point between the
output of digital interpolator filter and the input of the digital
decimator filter. See Figure 2.
RST (R/W, 1): Setting this bit to 1 will force a value of 0x00
to all digital processing stages.
PWDN (R/W, 1): Setting this bit to 1 will disable all data
processing for this codec and power down the associated
analog circuitry.
TxEN (R/W, 0): Setting this bit to 1 will enable the trans-
mitter on the codec. The transmitter is a differential mode
power stage. When disabled, the amplifier maintains a zero
differential output voltage (AO0+ = AO0– = VAG).
ALOCAL LOOP (R/W, 0): As opposed to the ALOOP bit of
this register, ALOCAL LOOP closes a local loopback at the
analog interface. When this bit is set active (1), the analog
output signal on pins AO0+ and AO0– is fed back into the in-
put amplifier stage on pins AI0+ and AI0–. See Figure 2.
Table 4. Register Map
Register Addr 7
6
5432
1
0 Mode
CNTL0_0 0x0
0 ANARSVD0 ALOOP0 DLOOP0
PWDN0
RST0
TxEN0
ALOCAL
LOOP
R/W
CNTL0_1 0x1 0 ANARSVD1 ALOOP1 DLOOP1 PWDN1
RST1
TxEN1
ALOCAL
LOOP
R/W
CNTL1_0 0x2 0 HPF_EN0
IN_GAIN0(1:0)
SPK_Rx0(1:0)
SPK_Tx0(1:0)
R/W
CNTL1_1
CNTL2_0
0x3
0x4
0 HPF_EN1
0 MCLK0_SEL
IN_GAIN1(1:0)
SPK_Rx1(1:0)
HSDIV0(5:0)
SPK_Tx1(1:0)
R/W
R/W
CNTL2_1
CNTL3_0
CNTL3_1
0x5
0x6
0x7
0 MCLK1_SEL
0
0
HSDIV1(5:0)
LSDIV0(6:0)
LSDIV1(6:0)
R/W
R/W
R/W
CNTL4
CNTL5
0x8
0x9
0
0
SWRESET RSVD
TEST_RSVD (1:0)
SSI_SEL
SYS_DIV(1:0)
SELF_CHECK (2:0)
SERIAL
LOOP
TEST_MODE (1:0)
R/W
RO
WO
CNTL6
CNTL7
0
0
RSVD (5:0)
RSVD (6:0)
WO
RO
WO
RO
SYNC 0xF 0
SEE DESCRIPTION
R/W
MOTOROLA
MC143416
11
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