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PDF MC14099BDW Data sheet ( Hoja de datos )
| Número de pieza | MC14099BDW | |
| Descripción | 8-Bit Addressable Latches | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC14099BDW (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14097B
See Page 150
8-Bit Addressable Latches
The MC14099B and MC14599B are 8–bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for writing into MC14599B. For the MC14599B the data pin is a
bidirectional data port and for the MC14099B the input is a unidirectional
write only port. The Write/Read line controls this port in the MC14599B.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip Enable.
A Master Reset capability is available on both parts.
• Serial Data Input
• Parallel Output
• Master Reset
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–Power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchottky TTL Load over the Rated Temperature Range
• MC14099B pin for pin compatible with CD4099B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
– 0.5 to + 18.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin, Iout Input or Output Current (DC or Transient),
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎper Pin
± 10
Unit
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
500 mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14099B
WRITE DISABLE
DATA
A0 5
A1
A2
6
7
DECODER
RESET
VDD = 16
VSS = 8
49
3 10
11
8
8
LATCHES
12
13
14
15
21
CHIP ENABLE
WRITE/READ
WRITE DISABLE
Q0
Q1
DATA
Q2
Q3
Q4
A0
A1
Q5 A2
Q6
Q7
RESET
MC14599B
8
10
4 11
3 12
8 13
5
6
7
8
DECODER
LATCHES
14
15
16
17
21
VDD = 18
VSS = 9
PIN ASSIGNMENT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN ASSIGNMENT
Q7 1
RESET 2
16 VDD
15 Q6
DATA
WRITE
DISABLE
A0
3
4
5
14 Q5
13 Q4
12 Q3
A1 6
A2 7
11 Q2
10 Q1
VSS 8
9 Q0
REV 0
1/94
©MMCot1or4o0la9, I9nBc. 1M99C514599B
246
Q7 1
RESET 2
DATA
WRITE
DISABLE
A0
3
4
5
A1 6
A2 7
CE 8
VSS 9
18 VDD
17 Q6
16 Q5
15 Q4
14 Q3
13 Q2
12 Q1
11 Q0
10
WRITE/
READ
MC14099B
MC14599B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14099BCP
MC14099BCL
MC14099BDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
L SUFFIX
CERAMIC
CASE 726
P SUFFIX
PLASTIC
CASE 707
ORDERING INFORMATION
MC14599BCP
MC14599BCL
Plastic
Ceramic
TA = – 55° to 125°C for all packages.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA
1 page  
RESET 2
DATA 3
VDD
MC14599B
FUNCTION DIAGRAM
11 Q0
VSS
CHIP
ENABLE
8
WRITE/READ 10
WRITE
DISABLE
4
A0 5
A1 6
A2 7
(M.S.B.)
TO
OTHER
LATCHES
ZERO
SELECT
EACH LATCH
ADDRESS
DECODER
OTHER LATCHES
12 Q1
13 Q2
14 Q3
15 Q4
16 Q5
17 Q6
1 Q7
TRUTH TABLE
Chip
Enable
Write/Read
Write
Disable
Reset
Addressed
Latch
0 X X0 *
1 1 0 0 Data
1 1 10 *
1 0 X0 *
X X X1 0
X = Don’t care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.
Other
Latches
*
*
*
*
0
Data
Pin
Z
Input
Z
Qn
Z/0
CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.
MC14099B MC14599B
250
MOTOROLA CMOS LOGIC DATA
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC14099BDW.PDF ] | |
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