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MC14011B の電気的特性と機能

MC14011BのメーカーはMotorola Semiconductorsです、この部品の機能は「B-Suffix Series CMOS Gates」です。


製品の詳細 ( Datasheet PDF )

部品番号 MC14011B
部品説明 B-Suffix Series CMOS Gates
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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MC14011B Datasheet, MC14011B PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
B-Suffix Series CMOS Gates
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
MC14XXXBD
Ceramic
SOIC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA = – 55° to 125°C for all packages.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎlin, lout
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
500 mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14001B
Quad 2-Input NOR Gate
MC14002B
Dual 4-Input NOR Gate
MC14011B
Quad 2-Input NAND Gate
MC14012B
Dual 4-Input NAND Gate
MC14023B
Triple 3-Input NAND Gate
MC14025B
Triple 3-Input NOR Gate
MC14068B
8-Input NAND Gate
MC14071B
Quad 2-Input OR Gate
MC14072B
Dual 4-Input OR Gate
MC14073B
Triple 3-Input AND Gate
MC14075B
Triple 3-Input OR Gate
MC14078B
8-Input NOR Gate
MC14081B
Quad 2-Input AND Gate
MC14082B
Dual 4-Input AND Gate
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14001B
7

1 Page





MC14011B pdf, ピン配列
MC14001B
Quad 2–Input NOR Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
PIN ASSIGNMENTS
MC14002B
Dual 4–Input NOR Gate
MC14011B
MC14012B
Quad 2–Input NAND Gate Dual 4–Input NAND Gate
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
MC14023B
MC14025B
Triple 3–Input NAND Gate Triple 3–Input NOR Gate
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
MC14068B
8–Input NAND Gate
NC 1
IN 1 2
IN 2 3
IN 3 4
IN 4 5
NC 6
VSS 7
14 VDD
13 OUT
12 IN 8
11 IN 7
10 IN 6
9 IN 5
8 NC
MC14071B
Quad 2–Input OR Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
MC14072B
Dual 4–Input OR Gate
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
MC14073B
Triple 3–Input AND Gate
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
MC14075B
Triple 3–Input OR Gate
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
MC14078B
8–Input NOR Gate
NC 1
IN 1 2
IN 2 3
IN 3 4
IN 4 5
NC 6
VSS 7
14 VDD
13 OUT
12 IN 8
11 IN 7
10 IN 6
9 IN 5
8 NC
MC14081B
Quad 2–Input AND Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
MC14082B
Dual 4–Input AND Gate
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
NC = NO CONNECTION
MOTOROLA CMOS LOGIC DATA
MC14001B
9


3Pages


MC14011B 電子部品, 半導体
1, 6, 8, 13
2, 5, 9, 12
3, 9
2, 10
5, 11
4, 12
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
One of Four Gates Shown
VDD
14
VDD
*
3, 4, 10, 11
7
VSS
* Inverter omitted in MC14001B
VSS
1, 3, 11
2, 4, 12
MC14002B, MC14072B
One of Two Gates Shown
VDD
MC14025B, MC14075B
One of Three Gates Shown
VDD
14 VDD
*
VSS
9, 6, 10
VDD
14 VDD
*
8, 5, 13
7 VSS
VSS
* Inverter omitted in MC14025B
VSS 1, 13
SAME AS
ABOVE
* Inverter omitted in MC14002B
7 VSS
2
3
VDD
MC14078B
Eight Input Gate
MC14001B
12
VSS
4 SAME AS
5 ABOVE
9 SAME AS
10 ABOVE
11 SAME AS
12 ABOVE
14 VDD
13
7 VSS
MOTOROLA CMOS LOGIC DATA

6 Page



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共有リンク

Link :


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