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TDA10085HT の電気的特性と機能

TDA10085HTのメーカーはNXP Semiconductorsです、この部品の機能は「Single chip DVB-S/DSS channel receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 TDA10085HT
部品説明 Single chip DVB-S/DSS channel receiver
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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TDA10085HT Datasheet, TDA10085HT PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
TDA10085HT
Single chip DVB-S/DSS channel
receiver
Product specification
Supersedes data of 2000 March 16
File under Integrated Circuits, IC02
2001 Aug 31

1 Page





TDA10085HT pdf, ピン配列
Philips Semiconductors
Single chip DVB-S/DSS channel receiver
Product specification
TDA10085HT
1 FEATURES
DSS and DVB-S compliant single chip demodulator and
forward error correction
Dual 6-bit Analog-to-Digital Converter (ADC) on-chip
PLL that allows using a low-cost crystal
(typically 4 MHz)
DiSEqC 1.X from 1 to 8 byte-long sequences with
modulated or unmodulated output
DSS dish control
Digital cancellation of ADC offset
Simultaneous parallel and serial output interfaces
Variable rate BPSK/QPSK coherent demodulator
Modulation rate variable from 1 to 49 Mbauds
Automatic gain control output
Digital symbol timing recovery:
– Acquisition range up to 960 ppm
Carrier offset cancellation up to one half of the sampling
frequency
Digital carrier recovery:
– Acquisition range up to 12% of the symbol rate
Half-Nyquist filters: roll-off = 0.35 for DVB and
0.2 for DSS
Interpolating and anti-aliasing filters to handle variable
symbol rates
Channel quality estimation
Spectral inversion ambiguity resolution
Viterbi decoder:
– Supported rates from 1/2 to 8/9
– Constraint length K = 7 with G1 = 1718 and
G2 = 1338
– Viterbi output BER measurement
– Automatic code rate search within 1/2, 2/3 and 6/7 in
DSS mode
– Automatic code rate search within 1/2, 2/3, 3/4, 5/6
and 7/8 in DVB-S mode
Convolutional de-interleaver and Reed Solomon
decoder according to DVB and DSS specifications
Automatic frame synchronization
Selectable DVB-S descrambling
I2C-bus interface
64-pin TQFP package
CMOS technology (0.2 µm, 1.8 V to 3.3 V).
2 APPLICATIONS
DVB-S receivers (ETS 300-421)
DSS receivers.
3 GENERAL DESCRIPTION
The TDA10085 is a single-chip channel receiver for
satellite television reception matching both DSS and
DVB-S standards. The device contains a dual 6-bit flash
ADC, variable rate BPSK/QPSK coherent demodulator
and forward error correction functions. The ADC interfaces
directly with I and Q analog baseband signals.
After analog-to-digital conversion, the TDA10085
implements a bank of cascadable filters as well as
anti-alias and half-Nyquist filters. An analog AGC signal is
generated using an amplitude estimation function. The
TDA10085 performs clock recovery at twice the baud rate
and achieves coherent demodulation without any
feedback to the local oscillator. Forward error correction is
built around two error-correcting codes: a Reed-Solomon
(outer code) and a Viterbi decoder (inner code). The
Reed-Solomon decoder corrects up to 8 erroneous bytes
among the N (204) bytes of one data packet.
A convolutional de-interleaver is located between the
Viterbi output and the Reed-Solomon decoder input. The
de-interleaver and Reed-Solomon decoder are
automatically synchronized according to a frame
synchronization algorithm that uses the sync pattern
present in each packet. The TDA10085 is controlled via an
I2C-bus interface. The circuit operates at sampling
frequencies up to 100 MHz, can process variable
modulation rates and achieves transmission rates up to
45 Mbaud. Furthermore, for dish control applications,
hardware supports DiSEqc 1.x with control access via the
I2C-bus.
An interrupt line that can be programmed to activate on
events or on timing information is provided.
Designed in 20 micron CMOS technology and housed in a
TQFP64 package, the TDA10085 operates over the
commercial temperature range.
2001 Aug 31
3


3Pages


TDA10085HT 電子部品, 半導体
Philips Semiconductors
Single chip DVB-S/DSS channel receiver
Product specification
TDA10085HT
SYMBOL
VDDI
VDDE
SDA_0
SCL_0
VAGC
PIN
26
27
28
29
30
CTRL3
SDA
SCL
TMS
TCK
TRST
31
32
33
34
35
36
FEL
VDDI
VSSI
TDI
37
38
39
40
2001 Aug 31
TYPE
supply
supply
I/OD
OD
O or OD
I/OD
I/OD
I
I/O
I/O
I/O
OD
supply
ground
I/O
DESCRIPTION
digital core supply voltage (typically 1.8 V)
digital supply voltage (typically 3.3 V)
I2C-bus bidirectional serial input/ open drain output; equivalent to
SDA but with a high-impedance state programmable via the I2C-bus;
a pull-up resistor must be connected between this pin and DVCC
I2C-bus clock output; equivalent to SCL but with a high-impedance
state programmable via the I2C-bus; open drain output requiring an
external pull-up resistor to 5 V
PWM encoded output signal for AGC; the refresh frequency of AGC
information is the sampling frequency divided by 2048, the maximum
signal frequency on the VAGC output is 1/4 × AGC sampling clock;
the VAGC output can be selected by I2C-bus to be open-drain or
have 3.3 V capability (typically, output VAGC is fed to the AGC
amplifier through a single RC network)
control line 3 input/open drain output; this pin function is directly
programmable through the I2C-bus interface and is an input by
default; it requires a pull-up resistor to 3.3 or 5 V, or a pull-down
resistor to GND
I2C-bus bidirectional serial data input/output; the open-drain output
requires a pull-up resistor (typically 2.2 k) to be connected between
SDA and 5 V for proper operation
I2C-bus clock input; nominally a square wave with a maximum
frequency of 400 kHz generated by the system I2C-bus master; see
note 1
boundary scan mode: test mode select input/output; provides the
logic levels needed to change the TAP controller from state to state
serial mode enabled (ENSERI = 1): serial TS uncorrectable output;
when not in serial mode, TMS must be set to VSS
boundary scan mode: test clock input/output; TCK is an independant
clock used to drive the TAP controller
serial mode enabled (ENSERI = 1): TCK is the serial TS clock
output; when not in serial mode, TCK must be set to VSS
boundary scan mode: test reset input/output; TRST is an active-LOW
reset input to the TAP controller
serial mode enabled (ENSERI = 1): test reset input/output; TRST is
the serial TS PSYNC output; when not in serial mode, TRST must be
set to VSS
front-end locked output signal that goes HIGH when demodulator,
Viterbi decoder and de-interleaver are all synchronized; open-drain
output requiring an external pull-up resistor to 3.3 or 5 V; can be set
via the I2C-bus to be an interrupt pin
digital core supply voltage (typically 1.8 V)
digital core ground voltage; see note 2
boundary scan mode: test data and instruction serial input
serial mode enabled (ENSERI = 1): serial TS data output; must be
set to VSS when not in serial mode
6

6 Page



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部品番号部品説明メーカ
TDA10085HT

Single chip DVB-S/DSS channel receiver

NXP Semiconductors
NXP Semiconductors


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