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PDF 74LCX138SJ Data sheet ( Hoja de datos )
| Número de pieza | 74LCX138SJ | |
| Descripción | Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1995
Revised March 1999
74LCX138
Low Voltage 1-of-8 Decoder/Demultiplexer
with 5V Tolerant Inputs
General Description
The LCX138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed memory chip
select address decoding. The multiple input enables allow
parallel expansion to a 1-of-24 decoder using just three
LCX138 devices or a 1-of-32 decoder using four LCX138
devices and one inverter.
The 74LCX138 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs
s 2.3V–3.6V VCC specifications provided
s 6.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Description
74LCX138M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LCX138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX138MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A2
E1–E2
E3
O0–O7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
© 1999 Fairchild Semiconductor Corporation DS012417.prf
www.fairchildsemi.com
1 page  
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH,tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable Times for Logic
trise and tfall
Symbol
3.3V ± 0.3V
VCC
2.7V
2.5V ± 0.2V
Vmi 1.5V
1.5V
VCC/2
Vmo 1.5V
1.5V
VCC/2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
FIGURE 2. Waveforms
(Input Pulse Characteristics; f=1MHz, tr=tf=3ns)
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74LCX138SJ.PDF ] | |
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