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74LCX112のメーカーはFairchild Semiconductorです、この部品の機能は「Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs」です。 |
部品番号 | 74LCX112 |
| |
部品説明 | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューと74LCX112ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
June 1998
Revised March 1999
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs
s 2.3V–3.6V VCC specifications provided
s 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 2000V
Ordering Code:
Order Number Package Number
Package Description
74LCX112M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LCX112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
© 1999 Fairchild Semiconductor Corporation DS012424.prf
www.fairchildsemi.com
1 Page Absolute Maximum Ratings(Note 1)
Symbol
Parameter
VCC Supply Voltage
VI DC Input Voltage
VO DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO
ICC
IGND
TSTG
DC Output Source/Sink Current
DC Supple Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to VCC + 0.5
−50
−50
+50
±50
±100
±100
−65 to 150
Conditions
Output in HIGH or LOW State (Note 2)
VI < GND
VO < GND
VO > VCC
Units
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Min
Max
Units
VCC Supply Voltage
Operating
Data Retention
2.0
1.5
3.6
3.6
V
VI Input Voltage
0 5.5 V
VO Output Voltage
HIGH or LOW State 0 VCC V
IOH/IOL Output Current
VCC = 3.0V − 3.6V
±24
VCC = 2.7V − 3.0V
±12 mA
VCC = 2.3V − 2.7V
±8
TA Free-Air Operating Temperature
−40 85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V−2.0V, VCC = 3.0V
0 10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 2: IO Absolute Maximum rating must be observed.
Note 3: Unused Inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II
IOFF
ICC
∆ICC
Input Leakage Current
Power-Off Leakage Current
Quiescent Supply Current
Increase in ICC per Input
Conditions
IOH = −100µA
IOH = -8 mA
IOH = −12 mA
IOH = −18 mA
IOH = −24 mA
IOL = 100µA
IOL = 8mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
0 ≤ II ≤ 5.5V
VI or VO = 5.5V
VI = VCC or GND
3.6V ≤ VI ≤ 5.5V
VIH = VCC −0.6V
VCC
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
2.7
3.0
3.0
2.3 − 3.6
2.3
2.7
3.0
3.0
2.3 − 3.6
0
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
TA = 40°C to +85°C
Min Max
1.7
2.0
0.7
0.8
VCC - 0.2
1.8
0.7
2.2
2.4
2.2
0.6
0.2
0.4
0.4
0.55
±5.0
10
10
±10
500
Units
V
V
V
V
µA
µA
µA
µA
µA
3 www.fairchildsemi.com
3Pages Schematic Diagram Generic for LCX Family
www.fairchildsemi.com
6
6 Page | |||
ページ | 合計 : 8 ページ | ||
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PDF ダウンロード | [ 74LCX112 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
74LCX11 | Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs | Fairchild Semiconductor |
74LCX112 | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs | Fairchild Semiconductor |
74LCX112M | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs | Fairchild Semiconductor |
74LCX112MTC | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs | Fairchild Semiconductor |