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74LCX00SJ の電気的特性と機能

74LCX00SJのメーカーはFairchild Semiconductorです、この部品の機能は「Low Voltage Quad 2-Input NAND Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74LCX00SJ
部品説明 Low Voltage Quad 2-Input NAND Gate
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74LCX00SJ Datasheet, 74LCX00SJ PDF,ピン配置, 機能
December 2013
74LCX00
Low Voltage Quad 2-Input NAND Gate
with 5V Tolerant Inputs
Features
5V tolerant inputs
2.3V–3.6V VCC specifications provided
5.2ns tPD max. (VCC = 3.3V), 10µA ICC max.
Power down high impedance inputs and outputs
±24mA output drive (VCC = 3.0V)
Implements proprietary noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model > 2000V
– Machine model > 200V
Leadless DQFN package
General Description
The LCX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX00 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Package
Order Number Number
Package Description
74LCX00M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX00SJ
74LCX00BQX(1)
M14D
MLP14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX00MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com

1 Page





74LCX00SJ pdf, ピン配列
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
Supply Voltage
DC Input Voltage
DC Output Voltage, Output in HIGH or LOW State(2)
DC Input Diode Current, VI < GND
DC Output Diode Current
VO < GND
VO > VCC
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
2. IO Absolute Maximum Rating must be observed.
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to VCC + 0.5V
–50mA
–50mA
+50mA
±50mA
±100mA
±100mA
–65°C to +150°C
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC Supply Voltage
Operating
Data Retention
VI
VO
IOH / IOL
TA
t / V
Input Voltage
Output Voltage, HIGH or LOW State
Output Current
VCC = 3.0V–3.6V
VCC = 2.7V–3.0V
VCC = 2.3V–2.7V
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
Min.
2.0
1.5
0
0
–40
0
Max.
3.6
3.6
5.5
VCC
±24
±12
±8
85
10
Units
V
V
V
mA
°C
ns /V
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
3
www.fairchildsemi.com


3Pages


74LCX00SJ 電子部品, 半導体
AC Loading and Waveforms (Generic for LCX Family)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH – 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH – 0.3V
2.5V ± 0.2V
VCC / 2
VCC / 2
VOL + 0.15V
VOH – 0.15V
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
6
www.fairchildsemi.com

6 Page



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部品番号部品説明メーカ
74LCX00SJ

Low Voltage Quad 2-Input NAND Gate

Fairchild Semiconductor
Fairchild Semiconductor


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