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PDF VT86C926 Data sheet ( Hoja de datos )
| Número de pieza | VT86C926 | |
| Descripción | AMAZON PCI ETHERNET CONTROLLER | |
| Fabricantes | ETC | |
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VT86C926
AMAZON
PCI ETHERNET CONTROLLER
DATA SHEET
(Preliminary)
DATE : June 27, 1995
VIA TECHNOLOGIES, INC.
1 page  
VIA TECHNOLOGIES, INC.
PRELIMINARY VT86C926
PIN DESCRIPTIONS
No. Name
PCI Bus Interface
98-100, 1- AD31-0
5, 8-13,
16-17,
26-33,
35-40,
43,44
95 PCICLK
96 INTA#
97 PCIRST#
6, 18, 25,
34
CBE#[3:0]
7 IDSEL
19 FRAME#
20 IRDY#
21 TRDY
22 DEVSEL#
23 STOP#
24 PAR
Type
Description
I/O Address/Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases. The
address phase is the clock cycle in which FRAME# is asserted. Write
data is stable and valid when IRDYB is asserted and read data is stable
and valid when TRDYB is asserted.
I PCICLK provides timing for all transactions on PCI and is an input pin
to every PCI device.
OD INTA# is an asynchronous signal which is used to request an interrupt
I When PCIRST# is asserted low, the VT86C926 chip performs an
internal system hardware reset. PCIRST# may be asynchronous to CLK
when asserted or deasserted. It is recommended that the deassertion be
synchronous to guarantee clean and bounce free edge.
I Bus Command/Byte Enables are multiplexed on the same PCI pins.
During the address phase of a transaction, CBE3-0B define the Bus
Command. Buring the data phase, CBE3-0B are used as Byte Enables.
The Byte Enables define which physical byte lanes carry meaningful
data. CBE0B applies to byte 0 and CBE3B applies to byte 3.
I Used as a chip select during PCI configuration cycle.
I Cycle Frame is driven by the current master to indicate the beginning
and duration of an access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is deasserted, the transaction is in the final
data phase.
I Initiator Ready indicates the initiating agent's ability to complete the
current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a write, IRDY# indicates that valid data is
present on AD31-0. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
I/O Target Ready indicates the target's agent's ability to complete the current
data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a read, TRDY# indicates that valid data is
present on AD31-0. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
I/O Device Select, when actively driven, indicates the driving device has
decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.
I/O VT86C926 drives STOP# to disconnect further traction.
T/S Parity is even parity across AD31-0 and CBE3-0B. PARis stable and
valid one clock after the address phase. For data phaases PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction.
5
5 Page 
VIA TECHNOLOGIES, INC.
6.4. PCI Configuration Space
PRELIMINARY VT86C926
Device ID
Vendor ID
( 0926 )
STATUS
(DEVS1, DEVS0 ) = ( 1 , 0 )
CLASS CODE
BIST
( 02_00_00 )
Header type
( 1106 )
COMMAND
( MMSPACE, IOSOACE)
Revision ID
Latency Timer
( 00 )
Cache Line
( 00 )
( 00 )
( 00 )
IO SPACE
( 00 )
0 0001
00 h
04 h
08 h
0c h
10 h
Reserved
Reserved
SUB Vendor ID
FR EEPROM contents
2c h
EXP ROM BASE [ 31: 15 ] ROM14 0000_0000_00000 EN 30 h
Reserved
Max_LAT
( 00 )
Min_GNT
( 00 )
INT PIN
( 01 )
Reserved
INTLINE
INTL [7:0]
3c h
6.5. Direct Programming of EEPROM
The VT86C926 features a easy way to program external EEPROM in-situ. When the RESET is active and
if the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current
EEPROM has not been programmed yet. This will allow the VT86C926 to enter Direct Programming
mode if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by
writing to the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS,
SK(MD2), and DI(MD1) outputs respectively. These outputs will be latched so the user can generate a
clock on SK by repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the
EEPROM signals as per the 93C46 data sheet.
To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as
described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data
Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the
EEPROM has been programmed and verified (remember to program the upper byte of 0EH with 73H), the
user must give VT86C926 a power-on reset to return to normal operation and to read in the new data.
The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once
the upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet VT86C926.PDF ] | |
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