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PDF VT82C586B Data sheet ( Hoja de datos )
| Número de pieza | VT82C586B | |
| Descripción | PCI INTEGRATED PERIPHERAL CONTROLLER | |
| Fabricantes | ETC | |
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1 page  
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VT82C586B
LIST OF FIGURES
FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C586B ................................................................................. 3
FIGURE 2. PIN DIAGRAM............................................................................................................................................................. 4
FIGURE 3. STRAP OPTION CIRCUIT....................................................................................................................................... 31
FIGURE 4. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 43
FIGURE 5. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 58
FIGURE 6. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................ 58
FIGURE 7. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ............................................................................... 59
FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND...... 60
FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND ... 60
FIGURE 10. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND...... 61
FIGURE 11. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND ... 61
FIGURE 12. ULTRADMA-33 IDE TIMING - PIO CYCLE ...................................................................................................... 62
FIGURE 13. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE.................................................. 63
Revision 1.0 May 13, 1997
-iii-
List of Figures
5 Page 
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VT82C586B
Signal Name
CPURST
INTR
NMI
INIT
STPCLK#
SMI#
FERR#
IGNNE#
Pin No.
142
145
146
143
148
149
141
139
Table 1. Pin Descriptions
CPU Interface
I/O Signal Description
O CPU Reset. The VT82C586B asserts CPURST to reset the CPU during power-up.
O CPU Interrupt. INTR is driven by the VT82C586B to signal the CPU that an
interrupt request is pending and needs service.
O Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the
CPU. The VT82C586B generates an NMI when either SERR# or IOCHK# is
asserted.
O Initialization. The VT82C586B asserts INIT if it detects a shut-down special cycle
on the PCI bus or if a soft reset is initiated by the register
O Stop Clock. STPCLK# is asserted by the VT82C586B to the CPU in response to
different Power-Management events.
O System Management Interrupt. SMI# is asserted by the VT82C586B to the CPU
in response to different Power-Management events.
O Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on
the CPU.
O Ignore Numeric Error. This pin is connected to the “ignore error” pin on the CPU.
Revision 1.0 May 13, 1997
-5-
Pinouts
11 Page | ||
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| PDF Descargar | [ Datasheet VT82C586B.PDF ] | |
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