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PDF VT8231 Data sheet ( Hoja de datos )

Número de pieza VT8231
Descripción SOUTH BRIDGE PC99 COMPLIANT
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! VT8231 Hoja de datos, Descripción, Manual

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VT8231 pdf
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VT8231
Function 4 Regs - Power Management, SMBus and HWM.............................................................................................. 83
PCI Configuration Space Header .......................................................................................................................................................... 83
Power Management-Specific PCI Configuration Registers .................................................................................................................. 84
Hardware-Monitor-Specific Configuration Registers ........................................................................................................................... 91
System Management Bus-Specific Configuration Registers ................................................................................................................. 91
Power Management I/O-Space Registers .............................................................................................................................................. 92
System Management Bus I/O-Space Registers.................................................................................................................................... 101
Hardware Monitor I/O Space Registers .............................................................................................................................................. 104
Function 5 & 6 Registers - AC97 Audio & Modem Codecs ............................................................................................ 108
PCI Configuration Space Header Function 5 Audio ........................................................................................................................ 108
PCI Configuration Space Header Function 6 Modem...................................................................................................................... 109
Function 5 & 6 Codec-Specific Configuration Registers .................................................................................................................... 110
Function 5 I/O Base 0 Regs DXSn Scatter/Gather DMA................................................................................................................. 112
Function 5 I/O Base 1 Registers Audio FM NMI Status................................................................................................................... 117
Function 5 I/O Base 2 Registers MIDI / Game Port.......................................................................................................................... 117
Function 6 I/O Base 0 Regs Modem Scatter/Gather DMA ............................................................................................................... 118
FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 120
POWER MANAGEMENT.............................................................................................................................................................. 120
Power Management Subsystem Overview .......................................................................................................................................... 120
Processor Bus States ........................................................................................................................................................................... 120
System Suspend States and Power Plane Control ............................................................................................................................... 121
General Purpose I/O Ports................................................................................................................................................................... 121
Power Management Events ................................................................................................................................................................. 122
System and Processor Resume Events ................................................................................................................................................ 122
Legacy Power Management Timers .................................................................................................................................................... 123
System Primary and Secondary Events ............................................................................................................................................... 123
Peripheral Events ................................................................................................................................................................................ 123
ELECTRICAL SPECIFICATIONS............................................................................................................................................. 124
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 124
DC CHARACTERISTICS.............................................................................................................................................................. 124
OUTPUT DRIVE .......................................................................................................................................................................... 125
INPUT VOLTAGE ........................................................................................................................................................................ 125
PACKAGE MECHANICAL SPECIFICATIONS ...................................................................................................................... 126
Preliminary Revision 0.8 October 29, 1999
-iii-
Table of Contents

5 Page





VT8231 arduino
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OVERVIEW
VT8231
The VT8231 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports
Intel, AMD, and VIA / Cyrix based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant PCI /
LPC system. The VT8231 includes standard intelligent peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT8231 also supports the UltraDMA-33, 66, and 100
standards to allow reliable data transfer rates up to 100 MB/sec throughput. The IDE controller is SFF-8038i v1.0 and
Microsoft Windows-family compliant.
b) Integrated LAN Fast Ethernet controller (MAC) with Media Independent Interface (MII) to external PHY. The LAN
controller operates at 1 / 10 / 100 Mbit/sec transfer rates using either full and half duplex operation and has separate 2Kbyte
FIFOs for receive and transmit of full ethernet packets. The internal high-performance PCI interface has scatter / gather and
bursting capability and can align bytes in the transmit data buffer to reduce CPU utilization. The LAN interface can perform
address filtering on physical, broadcast, and multicast packets. The interface can also be configured for system wake up on
link status change, receipt of magic packet, unicast physical address match on incoming packets, and predefined pattern
match in the incoming data.
c) LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support
d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub with
four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous
peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and
mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.
e) Keyboard controller with PS2 mouse support
f) Real Time Clock with 256 byte extended CMOS. In addition to standard RTC functionality, the integrated RTC also includes
the date alarm, century field, and other enhancements for compatibility with the ACPI standard.
g) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states
(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional
functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control,
modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip
select and external SMI.
h) Hardware monitoring subsystem for managing system / motherboard voltage levels, temperatures, and fan speeds
i) Full System Management Bus (SMBus) interface with one master / slave port and one slave-only port
j) 16550-compatible serial I/O port with Fast-IRinfrared communications port option.
k) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro and
hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback capability is
also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio.
l) Game port and MIDI port
m) Standard floppy disk drive interface
n) ECP/EPP-capable parallel port with floppy disk controller pinout option
o) Serial IRQ for docking and non-docking applications
p) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts to any interrupt channel.
One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of on-board peripherals for
Windows family compliance.
Preliminary Revision 0.8 October 29, 1999
-5-
Overview

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