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PDF VT6305 Data sheet ( Hoja de datos )
| Número de pieza | VT6305 | |
| Descripción | PCI 1394 Host Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VT6305 (archivo pdf) en la parte inferior de esta página. Total 35 Páginas | ||
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VT6305
PCI 1394 Host Controller
1394.A OHCI Link Layer Controller
for the PCI Bus
Revision 0.2
March 10, 2000
VIA TECHNOLOGIES, INC.
1 page  
Technologies, Inc.
We Connect
LIST OF FIGURES
FIGURE 1. VT6305 CHIP BLOCK DIAGRAM ..................................................................................................................... 2
FIGURE 2. VT6305 PIN DIAGRAM (TOP VIEW) ................................................................................................................ 3
FIGURE 3. VT6305 PIN LIST (ALPHABETICAL ORDER)................................................................................................. 4
FIGURE 4. MECHANICAL SPECIFICATIONS – 128 PIN PQFP PACKAGE ................................................................. 30
LIST OF TABLES
TABLE 1. VT6305 PIN DESCRIPTIONS ............................................................................................................................... 5
TABLE 2. REGISTERS ........................................................................................................................................................... 8
TABLE 3. PACKET EVENT CODES ................................................................................................................................... 25
Revision 0.2 March 10, 2000
-iii-
List of Figures & Tables
5 Page 
Technologies, Inc.
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Signal Name
PHYD[7:0]
PHYCTL1
PHYCTL0
PHYCLK
PHYLREQ
PHYLON
PHYLPS
Pin No.
114, 113, 112, 111,
109, 108, 107, 106
117
116
104
119
120
100
1394 PHY Interface
I/O Signal Description
IO PHY Data.
IO PHY Control 1.
IO PHY Control 0.
I PHY Clock.
O PHY Link Request.
I PHY Link On.
I PHY Link
Signal Name
EECS#
EEDO / MD0
EEDI / MD1
EECK / MD2
Pin No.
59
60
61
63
Serial Configuration Memory Interface
I/O Signal Description
O EEPROM Chip Select. Chip select for external serial EEPROM when used to
provide configuration data. A high-value pull-up resistor is provided internally.
O / I EEPROM Data Out.
I / I EEPROM Data In.
O / I EEPROM Clock.
Signal Name
MD[7:0]
MA[15:0]
MCS#
MRD#
MWR#
Pin No.
74
73
72
Local Memory Interface
I/O Signal Description
IO Memory Data. Pins optionally used for device bay if local memory not used
O Memory Address. Pins optionally used for device bay if local memory not used
O Memory Chip Select.
O Memory Read Enable.
O Memory Write Enable.
Signal Name
PME#
PCIISO
GPIO1 / DB0LEN
GPIO2 / DB3PEN
GPIO3 / DB3LEN
GPIO4
Pin No.
128
99
70
96
97
98
Miscellaneous
I/O
O
IO
IO / O
IO / O
IO / O
IO
Signal Description
Power Management Event.
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
Signal Name
Pin No.
Power and Ground
I/O Signal Description
Revision 0.2 March 10, 2000
-6-
Pinouts
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet VT6305.PDF ] | |
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