S2060D Datasheet PDF - ETC
| Part Number | S2060D | |
| Description | GIGABIT ETHERNET TRANSCEIVER | |
| Manufacturers | ETC | |
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DEVICE
SGPIEGCAIFBICITATEIOTNHERNET TRANSCEIVER
GIGABIT ETHERNET TRANSCEIVER
FEATURES
• Operating rate
• 1250 MHz (Gigabit Ethernet) line rates
• Half and full VCO output rates
• Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
• Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
• Receiver PLL provides clock and data recovery
• 10-bit parallel TTL compatible interface
• Low-jitter serial LVPECL compatible interface
• Local loopback
• Single +3.3 V supply, 620 mW power dissipation
• 64 PQFP or TQFP package
• Continuous downstream clocking from receiver
• Drives 30 m of Twinax cable directly
APPLICATIONS
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
®
S2060
S2060
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
Gigabit
Ethernet
Controller
S2060
Optical
Tx
Optical
Rx
Optical
Rx
Optical
Tx
S2060
Gigabit
Ethernet
Controller
March 7, 2001 / Revision H
1
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GIGABIT ETHERNET TRANSCEIVER
The COM_DET output signal is ACTIVE whenever
EN_CDET is active and the COMMA control charac-
ter is present on the RX[0:9] parallel data outputs.
The COM_DET output signal will be INACTIVE at all
other times.
Parallel Output Clock Rate and Data Stretching
The S2060 supports both full rate and half rate out-
puts, selected via the RATEN input. Table 4 shows
the operating rate scenarios. When RATEN is INAC-
TIVE, a data clock is provided on RBC1 at the data
rate. Data should be clocked on the rising edge of
RBC1. When RATEN is ACTIVE the device is in full
rate mode, and complementary TTL clocks are pro-
vided on the RBC0 and RBC1 outputs at 1/2 the
data rate as required by the Gigabit Ethernet Stan-
dard. Data is clocked on the rising edges of both
RBC0 and RBC1. See Figures 11 and 12.
Table 4. Operating Rates
RATEN
Serial Input
Rate (Gbps)
RBC0
(MHz)
0
1.25
62.5
1
.625
N/A
RCB1
(MHz)
62.5
62.5
Parallel
Output Rate
(Mbps)
125
62.5
S2060
Fibre Channel and Gigabit Ethernet Standards re-
quire that the COMMA sync character appears on
the rising edge of the RBC1 signal. In full rate mode
the phase of the data is adjusted such that this re-
quirement is met. No alignment is necessary when
the S2060 is operating in half rate mode since the
output clock frequency is equal to the parallel word
rate (RATEN INACTIVE).
In ethernet applications it is illegal for multiple con-
secutive COMMA characters to be generated. How-
ever, multiple consecutive COMMA characters can
occur in serial backplane applications. The S2060 is
able to operate properly when multiple consecutive
COMMA characters are received: after the first
COMMA is detected and aligned, the RBC0/RBC1
clock operates without glitches or loss of cycles.
Additionally, COM_DET stays high while multiple
COMMAS are being output.
Receive Latency
The average receive latency is 8 byte times.
March 7, 2001 / Revision H
5
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| Information | Total 22 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ S2060D.PDF Datasheet ] | |
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