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S2060B の電気的特性と機能

S2060BのメーカーはETCです、この部品の機能は「GIGABIT ETHERNET TRANSCEIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 S2060B
部品説明 GIGABIT ETHERNET TRANSCEIVER
メーカ ETC
ロゴ ETC ロゴ 




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S2060B Datasheet, S2060B PDF,ピン配置, 機能
DEVICE
SGPIEGCAIFBICITATEIOTNHERNET TRANSCEIVER
GIGABIT ETHERNET TRANSCEIVER
FEATURES
• Operating rate
• 1250 MHz (Gigabit Ethernet) line rates
• Half and full VCO output rates
• Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
• Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
• Receiver PLL provides clock and data recovery
• 10-bit parallel TTL compatible interface
• Low-jitter serial LVPECL compatible interface
• Local loopback
• Single +3.3 V supply, 620 mW power dissipation
• 64 PQFP or TQFP package
• Continuous downstream clocking from receiver
• Drives 30 m of Twinax cable directly
APPLICATIONS
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
®
S2060
S2060
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
Gigabit
Ethernet
Controller
S2060
Optical
Tx
Optical
Rx
Optical
Rx
Optical
Tx
S2060
Gigabit
Ethernet
Controller
March 7, 2001 / Revision H
1

1 Page





S2060B pdf, ピン配列
GIGABIT ETHERNET TRANSCEIVER
TRANSMITTER DESCRIPTION
The S2060 transmitter accepts 10-bit parallel input
data and serializes it for transmission over fiber optic
or coaxial cable media. The chip is fully compatible
with the IEEE 802.3z Gigabit Ethernet standard, and
supports the Gigabit Ethernet data rate of 1250.0
Mbps. The S2060 uses a PLL to generate the serial
rate transmit clock. The transmitter runs at 10 times
the TBC input clock, and operates in either full rate
or half rate mode. At the full VCO rate the transmitter
runs at 1.25 GHz, while in half rate mode it operates
at 625 MHz.
Parallel-to-Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the trans-
mitter on the positive going edge of TBC. The data is
then clocked into the serial output shift register. The
shift register is clocked by the internally generated
bit clock which is 10x the TBC input frequency. TX[0]
is transmitted first.
S2060
Transmit Byte Clock (TBC)
The Transmit Byte Clock input (TBC) must be sup-
plied from a clock source with 100 ppm tolerance to
assure that the transmitted data meets the Gigabit
Ethernet frequency limits. The internal serial clock is
frequency locked to TBC (125.00 MHz).
TBC may be 62.5 MHz or 125 MHz, determined by
the state of the RATEN input. Operating rates are
shown in Table 2.
Transmit Latency
The average transmit latency is 4 byte times.
Table 2. Operating Rates
RATEN
Parallel Input TBC Frequency
Rate (Mbps)
(MHz)
0 125
125
1 62.5
62.5
Serial Output
Rate (Gbps)
1.25
0.625
March 7, 2001 / Revision H
3


3Pages


S2060B 電子部品, 半導体
S2060
GIGABIT ETHERNET TRANSCEIVER
Table 5. Pin Description and Assignment
Pin Name
Level
I/O Pin #
Description
TX[9]
TX[8]
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
LVTTL
I
13 Transmit Data. Parallel data on this bus is clocked in on the
12 rising edge of TBC. TX[0] is transmitted first.
11
9
8
7
6
4
3
2
TBC
LVTTL
I
22 Transmit Byte Clock. Reference clock input to the PLL clock
multiplier. The frequency of TBC is the bit rate divided by 10.
When TESTEN is active, TBC replaces the VCO clock to
facilitate factory test. TBC should be supplied by a crystal
controlled reference since jitter on this line directly translates to
jitter on the output data.
RATEN
LVTTL
I
14 Rate Select. Active Low. This signal configures the PLL's for the
appropriate TBC frequency. When inactive, the device is in 1/2
rate mode. When active, the device is in full rate mode.
See Tables 2 and 4.
EN_CDET
LVTTL
I
24 Enable Comma Detect. Active High. When active, enables
detection of the COMMA sync pattern to set the word frame
boundary for the data to follow. When inactive, data is treated
as unframed.
EWRAP
LVTTL
I
19 Enable Wrap. When active, the transmitter serial data outputs
are internally routed to the receiver serial data inputs. TXP/N are
static (logic 1) in this state. When inactive, the RXP/N serial
inputs are selected (normal operation).
RXP
RXN
Diff.
LVPECL
I
54 (Externally Capacitively Coupled.) LVPECL Receive Serial Data
52 Inputs. RXP is the positive differential input, RXN is negative.
Internally biased to VCC -1.3 V.
-LCK_REF
LVTTL
I
27 Active Low. Lock to Reference Input. When inactive or open, the
receive PLL will lock to the incoming data (normal operation).
When active, the receive PLL is forced to lock to the TBC input.
6 March 7, 2001 / Revision H

6 Page



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共有リンク

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