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PDF V23815-U1306-M136 Data sheet ( Hoja de datos )

Número de pieza V23815-U1306-M136
Descripción PAROLI Tx AC/ 1.6 Gbit/s
Fabricantes Infineon Technologies 
Logotipo Infineon Technologies Logotipo



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No Preview Available ! V23815-U1306-M136 Hoja de datos, Descripción, Manual

Fiber Optics
Parallel Optical Link:
PAROLI ® Tx AC, 1.6 Gbit/s
Parallel Optical Link:
PAROLI ® Rx AC, 1.6 Gbit/s
V23814-U1306-M136
V23815-U1306-M136
Preliminary
Features
Power supply 3.3 V
Multistandard differential signal electrical interface
12 electrical data channels
Asynchronous, AC-coupled optical link
12 optical data channels
Transmission data rate of up to 1600 Mbit/s per
channel, total link data rate up to 19 Gbit/s
850 nm VCSEL array technology
PIN diode array technology
62.5 µm graded index multimode fiber ribbon
MT based optical port
SMD technology
IEC Class 1M laser safety compliant
GBE mask compliant modules available
Optical Port
Designed for the Simplex MT Connector (SMC)
Port outside dimensions: 15.4 mm x 6.8 mm (width x height)
MT compatible (IEC 61754-5) fiber spacing (250 µm) and
alignment pin spacing (4600 µm)
Alignment pins fixed in module port
Integrated mechanical keying
Process plug (SMC dimensions) included with every module
PAROLI® is a registered trademark of Infineon Technologies AG
Data Sheet
1
2002-05-14

1 page




V23815-U1306-M136 pdf
V23814-U1306-M136
V23815-U1306-M136
Pin Configuration
Pin Description Transmitter (contd)
Pin Symbol Level/Logic Description
No.
43 VEE
44 VEE
45 VEE
46 DI09N Data In
Ground
Ground
Ground
Data Input #9, inverted
47 DI09P Data In
Data Input #9, non-inverted
48 t.b.l.o.
to be left open
49 VEE
50 VEE
51 DI10N Data In
Ground
Ground
Data Input #10, inverted
52 DI10P Data In
Data Input #10, non-inverted
53 VEE
54 VEE
55 DI11N Data In
Ground
Ground
Data Input #11, inverted
56 DI11P Data In
Data Input #11, non-inverted
57 VEE
58 VEE
59 DI12N Data In
Ground
Ground
Data Input #12, inverted
60 DI12P Data In
Data Input #12, non-inverted
61 VEE
62 VIN
63 t.b.l.o.
Ground
Input VIN rail.
CML: VIN = Reference supply (e.g. VCC).
LVPECL, LVDS: VIN = VEE.
to be left open
64 RESET LVCMOS In High = laser diode array is active.
Low = switches laser diode array off.
This input has an internal pull-down to ensure laser
safety switch off in case of unconnected RESET
input.
65 VEE
66 VEE
Ground
Ground
Data Sheet 5 2002-05-14

5 Page





V23815-U1306-M136 arduino
V23814-U1306-M136
V23815-U1306-M136
Description
Receiver V23815-U1306-M136
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, transimpedance amplifiers, and gain amplifiers. There are two different modules
available for LVDS and Infineons adjustable CML output. This description only refers to
a module with LVDS output. A module description for CML output can be provided
separately.
The data rate is up to 1600 Mbit/s for each channel. The receiver modules min. data rate
of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with
a lower disparity.
Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs
will not be effected.
All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is
at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per
meter for the fiber optic cable.
Optical
Input
12
Data
12
Pin
Diode
Array
Amplifier
Electrical
Output
Gain
12
Amplifier
12
LVDS
Output
Stage
Data out
Signal
Detect
Circuit
SD1
-SD12
ENSD Output Enable (OEN)
Figure 3 Receiver Block Diagram
1) Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Data Sheet
11
2002-05-14

11 Page







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