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VG4632321A の電気的特性と機能

VG4632321AのメーカーはVanguard International Semiconductorです、この部品の機能は「524/288x32x2-Bit CMOS Synchronous Graphic RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 VG4632321A
部品説明 524/288x32x2-Bit CMOS Synchronous Graphic RAM
メーカ Vanguard International Semiconductor
ロゴ Vanguard International Semiconductor ロゴ 




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VG4632321A Datasheet, VG4632321A PDF,ピン配置, 機能
VIS
Overview
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4632321A SGRAM is a high-speed CMOS synchronous graphic RAM containing 32M bits. It is
internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 512K x 32 bit bank is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4632321A provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with
burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy
to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Pin Assignment (Top View)
Features
• Fast access time from clock: 4.5/5/5.5/6/7ns
• Fast clock rate: 222/200/183/166/143MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(512K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V ±0.3V power supply
• Interface: LVTTL
• JEDEC 100-pin Plastic QFP package
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE
CAS
RAS
CS
BS
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Key Specifications
VG4632321A
tCK Clock Cycle time(min.)
tRAS
Row Active time(min.)
tAC Access time from CLK(max.)
tRC Row Cycle time(min.)
-4.5/-5/-5.5/-6/-7
4.5/5/5.5/6/7 ns
40/40/40/42/42 ns
4/4.5/5/5.5/6 ns
55/55/56.5/60/62 ns
80 DQ28
79 VDDQ
78 DQ27
77 DQ26
76
75
VSSQ
DQ25
74 DQ24
73
72
VDDQ
DQ15
71 DQ14
70 VSSQ
69 DQ13
68 DQ12
67 VDDQ
66 VSS
65 VDD
64 DQ11
63 DQ10
62 VSSQ
61 DQ9
60 DQ8
59
58
VDDQ
NC
57 DQM3
56 DQM1
55 CLK
54 CKE
53 DSF
52 NC
51 A8/AP
Document:
Rev.1
Page 1

1 Page





VG4632321A pdf, ピン配列
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Table 1 shows the details for pin number, symbol, type, and description.
Table 1. Pin Description of VG4632321A
Pin Num- Symbol
ber
55 CLK
54 CKE
29 BS
30-34, A0-A10
45,47-51
28 CS
27 RAS
26 CAS
25 WE
53 DSF
Type Description
Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
control the output registers.
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE
goes low synchronously with clock (set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When both banks are in
the idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during Power Down
and Self Refresh modes providing low standby power.
Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or Bank-
Precharge command is being applied. BS is also used to program the 10th bit of
the Mode and Special Mode registers.
Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A8
defining Auto Precharge) to select one location out of the 512K available in the
respective bank. During a Precharge command, A8 is sampled to determine if both
banks are to be precharged (A8 = HIGH). The address inputs also provide the
op-code during a Mode Register Set or Special Mode Register Set command.
Input
Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS is sampled HIGH. CS
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Input
Row Address Strobe: The RAS signal defines the operation commands in
conjunction with the CAS and WE signals, and is latched at the positive edges of
CLK. When RAS and CS are asserted “LOW” and CAS is asserted “HIGH”, either
the BankActivate command or the Precharge command is selected by the WE
signal. When the WE is asserted “HIGH” the BankActivate command is selected
and the bank designated by BS is turned on to the active state. When the WE is
asserted "LOW", the Precharge command is selected and the bank designated by
BS is switched to the idle state after precharge operation.
Input
Column Address Strobe: The CAS signal defines the operation commands in
conjunction with the RAS and WE signals, and it is latched at the positive edges of
CLK. When RAS is held “HIGH” and CS is asserted “LOW”, the column access is
started by asserting CAS “LOW”. Then, the Read or Write command is selected by
asserting WE “LOW” or “HIGH”.
Input
Write Enable: The WE signal defines the operation commands in conjunction with
the RAS and CAS signals, and it is latched at the positive edges of CLK. The WE
input is used to select the BankActivate or Precharge command and Read or Write
command.
Input
Define Special Function: The DSF signal defines the operation commands in
conjunction with the RAS and CAS and WE signals, and it is latched at the positive
edges of CLK. The DSF input is used to select the masked write disable/enable
command and block write command, and the Special Mode Register Set cycle.
Document:
Rev.1
Page 3


3Pages


VG4632321A 電子部品, 半導体
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Commands
1 BankActivate & Masked Write Disable command
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”L”, BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By
latching the row address on A0 to A10 at the time of this command, the selected row access is initiated.
The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of
bank activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by tRC(min.).
The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce
chip area, therefore it restricts the back-to-back activation of both banks. tRRD(min.) specifies the
minimum time required between activating different banks. After this command is used, the Write
command and the Block Write command perform the no mask write operation.
T0 T1 T2 T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Row Addr.
Bank A
Col Addr.
Bank A
Row Addr.
COMMAND
RAS-CAS delay (tRCD)
Bank A
Activate
NOP
NOP
R/W A with
AutoPrecharge
RAS-RAS delay time (tRRD)
Bank B
Activate
NOP
NOP
RAS Cycle time (tRC)
: “H” or “L”
AutoPrecharge
Begin
BankActivate Command Cycle (Burst Length = n, CAS Latency = 3)
Bank A
Row Addr.
Bank A
Activate
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”H”, BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this command is
performed, the Write command and the Block Write command perform the masked write operation. In
the masked write and the masked block write functions, the I/O mask data that was stored in the write
mask register is used.
3 BankPrecharge command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Bank, A8 = ”L”, A0-A7,A9,A10 = Don’t care)
The BankPrecharge command precharges the bank designated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in
any active bank within tRAS(max.). At the end of precharge, the precharged bank is still the idle state and
ready to be activated again.
4 PrechargeAll command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Don’t care, A8 = ”H”, A0-A7,A9,A10 = Don’t care)
The PrechargeAll command precharges both banks simultaneously. Even if both banks are not in
the active state, the PrechargeAll command can be issued. Both banks are then switched to the idle
state.
5 Read command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A8 = ”L”, A0-A7 = Column Address, A9,A10 = Don’t
care)
Document:
Rev.1
Page 6

6 Page



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部品番号部品説明メーカ
VG4632321A

524/288x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor


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