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VG4616322BQ-6R の電気的特性と機能

VG4616322BQ-6RのメーカーはVanguard International Semiconductorです、この部品の機能は「262/144x32x2-Bit CMOS Synchronous Graphic RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 VG4616322BQ-6R
部品説明 262/144x32x2-Bit CMOS Synchronous Graphic RAM
メーカ Vanguard International Semiconductor
ロゴ Vanguard International Semiconductor ロゴ 




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VG4616322BQ-6R Datasheet, VG4616322BQ-6R PDF,ピン配置, 機能
VIS
Overview
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It
is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by
256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page,
with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh
are easy to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
• Fast access time from clock: 4.5/5/5.5ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(256K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V ±0.3V power supply
• Input Reference Voltage : Vref = 1.5V ± 0.2V
• Interface: LVTTL and SSTL_3
• JEDEC 100-pin Plastic QFP package
Document:1G5-0145
Rev.1
Page 1

1 Page





VG4616322BQ-6R pdf, ピン配列
VIS
Block Diagram
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
CKE
CS
RAS
CAS
WE
DSF
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
A9
A0 ADDRESS
BUFFER
A8
BS
REFRESH
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
SPECIAL
MODE
REGISTER
Column Decoder
1024 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Amplifier
COLOR
REGISTER
MASK
REGISTER
DQs
BUFFER
DQM0~3
DQ0
|
DQ31
Sense Amplifier
1024 X 256 X 32
CELL ARRAY
(BANK #1)
Column Decoder
Document:1G5-0145
Rev.1
Page 3


3Pages


VG4616322BQ-6R 電子部品, 半導体
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note(1), (2))
Command
State CKEn-1 CKEn DQM(7) BS A9 A0-8 CS RAS CAS WE DSF
BankActivate & Masked Write Disable Idle(3)
H X X V VVL L HHL
BankActivate & Masked Write Enable
Idle(3)
H X X V VVL L HHH
BankPrecharge
Any H X X V L X L L H L L
PrechargeAll
Any H X X X H X L L H L L
Write
Active(3)
H
X X V LVLHL LL
Block Write Command
Active(3)
H
X X V LVLHL LH
Write and AutoPrecharge
Active(3)
H
X X V HVL H L L L
Block Write and AutoPrecharge
Active(3)
H
X X V HVL H L L H
Read
Active(3)
H
X X V LVLHLHL
Read and AutoPrecharge
Active(3)
H
X X V HVL H L HL
Mode Register Set
Idle H X X V L V L L L L L
Special Mode Register Set
Idle(5)
H X X X XVL L L LH
No-Operation
Any H X X X X X L H H H X
Burst Stop
Active(4)
H
X X X XXL HHL L
Device Deselect
Any H X X X X X H X X X X
AutoRefresh
Idle H H X X X X L L L H L
SelfRefresh Entry
Idle H L X X X X L L L H L
SelfRefresh Exit
Idle
(SelfRefresh)
L
H X X XXH X XXX
L HHHX
Clock Suspend Mode Entry
Active
H L X X XXX XXXX
Power Down Mode Entry
Any(6)
H L X X XXH X XXX
L HHHL
Clock Suspend Mode Exit
Active
L H X X XXX XXXX
Power Down Mode Exit
Any L H X X X X H X X X X
(Power-
Down)
L HHHL
Data Write/Output Enable
Active
H X L X XXX XXXX
Data Write/Output Disable
Active
H X H X XXX XXXX
Note: 1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Document:1G5-0145
Rev.1
Page 6

6 Page



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部品番号部品説明メーカ
VG4616322BQ-6

262/144x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor
VG4616322BQ-6R

262/144x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor


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