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VG36648041BT-10 の電気的特性と機能

VG36648041BT-10のメーカーはVanguard International Semiconductorです、この部品の機能は「CMOS Synchronous Dynamic RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 VG36648041BT-10
部品説明 CMOS Synchronous Dynamic RAM
メーカ Vanguard International Semiconductor
ロゴ Vanguard International Semiconductor ロゴ 




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VG36648041BT-10 Datasheet, VG36648041BT-10 PDF,ピン配置, 機能
VIS
Description
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V ( ±0.3V) power supply
• High speed clock cycle time : 7/8ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X8 organization
• Input/Output controlled by DQM
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0153
Rev.1
Page 1

1 Page





VG36648041BT-10 pdf, ピン配列
VIS
Block Diagram
CLK
CKE
Clock
Generator
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Address
CS
RAS
CAS
WE
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ
Document : 1G5-0153
Rev.1
Page 3


3Pages


VG36648041BT-10 電子部品, 半導体
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
A. C Characteristics : (Ta = 0 to 70°C V DD = 3.3V ± 0.3VSS = 0V)
Test Conditions for LVTTL Compatible :
AC input Levels (VIH/VIL)
Input rise and fall time
2.0/0.8V
1ns
Input timing reference level/
Output timing reference level
Output load condition
1.4V
50pF
AC Test Load Circuits (for LVTTL interface) :
VDDQ
VOUT
Device
Under
Test
VDDQ
Z = 50
50PF
Document : 1G5-0153
Rev.1
Page 6

6 Page



ページ 合計 : 30 ページ
 
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部品番号部品説明メーカ
VG36648041BT-10

CMOS Synchronous Dynamic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor


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