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PDF VES9600 Data sheet ( Hoja de datos )
| Número de pieza | VES9600 | |
| Descripción | SINGLE CHIP DVB-T CHANNEL RECEIVER | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VES9600 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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PRELIMINARY
VES9600
SINGLE CHIP
DVB-T
CHANNEL RECEIVER
FEATURES
• 2K and 8K COFDM demodulator ( Fully
DVB-T compliant : ETS 300-744).
• All modes supported including
hierarchical modes.
• On chip 9-bit ADC.
• Digital down conversion.
• Fully automatic transmission parameters
detection.
• Crystal or VCXO clock generation.
• Frequency offset estimator to speed up
the scan.
• RF Tuner input power measurement
• On chip FEC decoder, full DVB-T
compliant.
• Parallel or serial transport stream
interface.
• DSP based synchronization.
• BER measurement
• SNR estimation
• Channel frequency response output.
• Channel impulse response output.
• Controllable dedicated I2C tuner bus.
• 2 low frequency spare DAC. (∆Σ)
• Spare I/O.
• I2C bus interface, for easy control.
• CMOS 0.35µm technology.
DESCRIPTION
The VES9600 is a single chip channel receiver for 2K and 8K
COFDM modulated signals based on the ETSI specification (ETSI
300 744). The device interfaces directly to an IF signal, which is
sampled by a 9-bit AD converter.
The VES9600 performs all the COFDM demodulation tasks from IF
signal to the MPEG2 transport stream. An internal DSP core
manages the synchronization and the control of the demodulation
process.
After base band conversion and FFT, the channel frequency
response is estimated based on the scattered pilots, and filtered in
both time and frequency domains. This estimation is used as a
correction on the signal, carrier by carrier. A common phase error
and estimator is used to deal with the tuner phase noise.
The FEC decoder is automatically synchronized thanks to the frame
synchronization algorithm that uses the TPS information included in
the modulation. Finally descrambling according to DVB-T standard,
is achieved at the Reed Solomon output.
This device is controlled via an I2C bus. The chip provides a
switchable tuner I2C bus to be disconnected from the I2C master
when not necessary. The DSP software code can be fed to the
chip via the master I2C bus or via a dedicated I2C bus (Eeprom).
Designed in 0.35 µm CMOS technology and housed in a 208-pin
MQFP package, the VES9600 operates over the commercial
temperature range.
APPLICATIONS
• DVB-T fully compatible.
• Digital data transmission using
COFDM modulations.
VLSI/comatlas reserves the right to make any change at anytime without notice.
VES 9600 rev 1.2 / Sep 99
1 page  
IT
76
O
(5V)
Interrupt line. This output interrupt line can be configured by the I2C
interface. See registers Itsel and Itstat. IT is an open drain output and
therefore requires an external pull up resistor.
DO[7:0]
OCLK
DEN
PSYNC
UNCOR
FSTART
DVIT
HVIT
118-119-120-
121-124-125-
126-127
113
115
112
114
109
108
107
O
(3.3)
O
(3.3)
O
(3.3)
O
(3.3)
O
(3.3)
O
(3.3)
O
(3.3)
O
(3.3)
FEC OUTPUTS
output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default. When
the serial mode is selected, the output data is delivered by DO[0].
Output CLock. OCLK is the output clock for the parallel DO[7:0]
outputs. OCLK is internally generated depending on which interface is
selected.
output data validation signal active high during the valid and regular
data bytes (may be inverted, see serial bus description).
Pulse SYNChro. This output signal goes high on a rising edge of
OCLK when a synchro byte is provided, then goes low until the next
synchro byte (may be inverted).
RS error flag, active high on one RS packet if the RS decoder fails in
correcting the errors (may be inverted).
Frame start active high for one OCLK output clock cycle at the
beginning of a new superframe made of 272 OFDM symbols for the 2k
mode and made of 68 OFDM symbols for the 8k mode (may be
inverted as C3_psync).
viterbi output data stream, delivered on the rising hedge of HVIT. You
can also find the viterbi output on DO[0] after by-passing the RS and
the descrambling.
viterbi output data stream clock, according to DVIT.
VIM
VIP
CMCAP
RBIAS
CMI
CMO
VREF
VREFP
ON-CHIP ADC SIGNALS
48 Negative input to the A/D converter. This pin is DC biased to half
I
supply through an internal resistor divider (2x10K resistors). In order
to remain in the range of the ADC, the voltage difference between pins
VIP and VIM should be between -0.5 and 0.5 volts.
49 Positive input to the A/D converter. This pin is DC biased to half supply
I
through an internal resistor divider (2x10K resistors). In order to
remain in the range of the ADC, the voltage difference between pins
VIP and VIM should be between –0.5 and 0.5 volts.
42 This pin is connected to a tap point on an internal resistor divider used
I
to create CMO and CMI. An external capacitor of value 0.1µf should
be connected between this point and ground to provide good power
supply rejection from the positive supply at higher frequencies.
39 An external resistor of value 3.3k should be connected between this
I pin and ground to provide good accurate bias currents for the analog
circuits on the ADC.
40 This pin provides the common-mode in voltage for the analog circuits
O on the ADC. It is the buffered version of a voltage derived from an on-
chip resistor devider, and has a nominal value of 0.75 x VD3.
41 This pin provides the common-mode out voltage for the analog circuits
O on the ADC. It is the buffered version of a voltage derived from an on-
chip resistor devider, and has a nominal value of 0.5 x VD3.
45 This is the output of an on-chip resistor divider. An external capacitor
of value 0.1µf should be connected between this point and ground to
O provide good power supply rejection from the positive supply at higher
frequencies. Reference voltages VREFP and VREFM are derived from
the voltage on VREF.
44 O This is a positive voltage reference for the A/D converter. It is derived
VLSI/comatlas reserves the right to make any change at anytime without notice. VES 9600 rev 1.2 / Oct 99 / p5
5 Page 
PACKAGE INFORMATION
NOTE : Dimensions are in millimeters
VLSI/comatlas reserves the right to make any change at anytime without notice. VES 9600 rev 1.2 / Oct 99 / p11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet VES9600.PDF ] | |
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