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V827332U04S の電気的特性と機能

V827332U04SのメーカーはMosel Vitelic Corpです、この部品の機能は「2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE」です。


製品の詳細 ( Datasheet PDF )

部品番号 V827332U04S
部品説明 2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V827332U04S Datasheet, V827332U04S PDF,ピン配置, 機能
MOSEL VITELIC
V827332U04S
2.5 VOLT 32M x 72 HIGH PERFORMANCE
REGISTERED ECC DDR SDRAM MODULE
PRELIMINARY
Features
184 Pin Registered 33,554,432 x 72 bit
Organization DDR SDRAM Modules
Utilizes High Performance 16M x 8 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V (± 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
4096 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Component Used -7 -75 -8 Units
tCK Clock Frequency
(max.)
143 133 125 MHz
(PC266A) (PC266B) (PC200)
tAC Clock Access Time
7
7.5
8 ns
CAS Latency = 2.5
Description
The V827332U04S memory module is organized
33,554,432 x 72 bits in a 184 pin memory module.
The 32M x 72 memory module uses 18 Mosel-
Vitelic 16M x 8 DDR SDRAM. The x72 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.
Module Speed
A1 PC1600 (100MHz @ CL2)
B0 PC2100B (133MHz @ CL2.5)
B1 PC2100A (133MHz @ CL2)
Reg PLL Reg
V827332U04S Rev. 1.2 March 2002
1

1 Page





V827332U04S pdf, ピン配列
MOSEL VITELIC
Block Diagram
V827332U04S
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQS8
DM8
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0
CS1
BA0-BAN
A0-A11
RAS
CAS
CKE0
CKE1
WE
PCK
PCK
R
E
G
I
S
T
E
R
RS0
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D0
CS DQS
D1
CS DQS
D2
CS DQS
D3
RS1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS4
DM4/DQS13
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
CS DQS
D10
CS DQS
D11
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
CS DQS
D12
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D13
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D14
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D8
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D17
SPD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
Strap: see Note 4
RCS0
RCS1
RBA0 - RBAn
RA0 - RA11
RRAS
RCAS
RCKE0
RCKE1
RWE
BA0 -BAn : SDRAMs DQ0 - D17
A0 -An : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17
RESET
SCL
WP
Serial PD
A0 A1 A2
SA0 SA1 SA2
SDA
CK0,CK0
PLL*
* Wire per Clock Loading table/wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD VDDQ.
V827332U04S Rev. 1.2 March 2002
3


3Pages


V827332U04S 電子部品, 半導体
MOSEL VITELIC
V827332U04S
Serial Presence Detect Information (cont.)
Byte #
Function described
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module ROW density
32 Command and address signal input setup time
33 Command and address signal input hold time
34 Data signal input setup time
35 Data signal input hold time
36-40 Superset information (may be used in future)
41
42
43
44
45
46-61
SDRAM device minimum active to active/auto-refresh time
(=tRC)
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=tRFC)
SDRAM device maximum device cycle time (=tCK MAX)
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
SDRAM device maximum read datahold skew factor (=tQHS)
Superset information (may be used in future)
62 SPD data revision code
63 Checksum for Bytes 0 ~ 62
64 Manufacturer JEDEC ID code
65 -71 ....... Manufacturer JEDEC ID code
72 Manufacturing location
73-90 Module part number (ASCII)
91 Manufacturer revison code (For PCB)
92 Manufacturer revison code (For component)
93 Manufacturing date (Week)
94 Manufacturing date (Year)
95~98 Assembly serial #
99~127 Manufacturer specific data (may be used in future)
128~255 Open for customer use
Function Supported
A1 B0 B1
20ns 20ns 18ns
50ns 45ns 45ns
128MB
1.1ns 0.9ns 0.9ns
1.1ns 0.9ns 0.9ns
0.6ns 0.5ns 0.5ns
0.6ns 0.5ns 0.5ns
-
70ns 65ns 60ns
Hex value
A1 B0 B1
50h 50h 48h
32h 2Dh 2Dh
20h
B0h 90h 90h
B0h 90h 90h
60h 50h 50h
60h 50h 50h
00h
46h 41h 3Ch
80ns 75ns 67ns 50h 4Bh 43h
12ns 12ns 12ns 30h 30h 30h
0.6ns 0.5ns 0.5ns 3Ch 32h 32h
1ns 0.75ns 0.75ns A0h 75h 75h
- 00h
Initial release
00h
- DDh 23h C2h
Mosel Vitelic
40h
Mosel Vitelic
00h
01h
V827332U04S
0 00
0 00
--
--
--
Undefined
00h
Undefined
00h
V827332U04S Rev. 1.2 March 2002
6

6 Page



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部品番号部品説明メーカ
V827332U04S

2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE

Mosel Vitelic  Corp
Mosel Vitelic Corp


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