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PDF V826632K24S Data sheet ( Hoja de datos )
| Número de pieza | V826632K24S | |
| Descripción | 2.5 VOLT 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V826632K24S
2.5 VOLT 32M x 64 HIGH PERFORMANCE
UNBUFFERED DDR SDRAM MODULE
PRELIMINARY
Features
■ 184 Pin Unbuffered 33,554,432 x 64 bit
Organization DDR SDRAM Modules
■ Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
Component Used B1 B0 A1 Units
tCK Clock Frequency 143 133 125 MHz
(max.)
(PC266A) (PC266B) (PC200)
tAC Clock Cycle Time
7
7.5
8 ns
CAS Latency = 2.5
Description
The V826632K24S memory module is organized
33,554,432 x 64 bits in a 184 pin memory module.
The 16M x 64 memory module uses 8 Mosel-Vitelic
32M x 8 DDR SDRAM. The x64 modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
V826632K24S Rev. 1.0 April 2002
1
1 page  
MOSEL VITELIC
Serial Presence Detect Information
Bin Sort:
B1 (PC266A @ CL = 2)
B0 (PC266B @ CL = 2.5)
A1 (PC200 @ CL = 2)
V826632K24S
Function Supported
Hex value
Byte #
Function described
A1 B0 B1 A1 B0 B1
0 Defines # of Bytes written into serial memory at module manufacturer
128bytes
80h
1 Total # of Bytes of SPD memory device
256bytes
08h
2 Fundamental memory type
SDRAM DDR
07h
3 # of row address on this assembly
13 0Dh
4 # of column address on this assembly
10 0Ah
5 # of module Rows on this assembly
1 Bank
01h
6 Data width of this assembly
64 bits
40h
7 .........Data width of this assembly
- 00h
8 VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9 DDR SDRAM cycle time at CAS Latency =2.5
8ns 7.5ns 7ns 80h 75h 70h
10 DDR SDRAM Access time from clock at CL=2.5
±0.8ns ±0.75ns ±0.75ns 80h 75h 75h
11 DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00h
12 Refresh rate & type
7.8us & Self refresh
82h
13 Primary DDR SDRAM width
x8 08h
14 Error checking DDR SDRAM data width
N/A 00h
15 Minimum clock delay for back-to-back random column
address
tCCD=1CLK
01h
16 DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17 DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18 DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19 DDR SDRAM device attributes : CS Latency
0CLK
01h
20 DDR SDRAM device attributes : WE Latency
1CLK
02h
21 DDR SDRAM module attributes
Differential clock /
non Registered
20h
22 DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23 DDR SDRAM cycle time at CL =2
10ns 10ns 7.5ns A0h A0h 75h
24 DDR SDRAM Access time from clock at CL =2
±0.8ns ±0.75ns ±0.75ns 80h 75h 75h
25 DDR SDRAM cycle time at CL =1.5
---
00h
26 DDR SDRAM Access time from clock at CL =1.5
---
00h
27 Minimum row precharge time (=tRP)
28 Minimum row activate to row active delay(=tRRD)
20ns 20ns 20ns 50h 50h 50h
15ns 15ns 15ns 3Ch 3Ch 3Ch
V826632K24S Rev.1.0 April 2002
5
5 Page 
MOSEL VITELIC
Absolute Maximum Ratings
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature • Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Note: Operation at above absolute maximum rating can adversely affect device reliability
V826632K24S
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
6
260 • 10
Unit
°C
°C
V
V
V
mA
W
°C • Sec
V826632K24S Rev.1.0 April 2002
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet V826632K24S.PDF ] | |
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