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V62C5181024LL-70P の電気的特性と機能

V62C5181024LL-70PのメーカーはSamsung semiconductorです、この部品の機能は「2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL」です。


製品の詳細 ( Datasheet PDF )

部品番号 V62C5181024LL-70P
部品説明 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
メーカ Samsung semiconductor
ロゴ Samsung semiconductor ロゴ 




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V62C5181024LL-70P Datasheet, V62C5181024LL-70P PDF,ピン配置, 機能
K4S643232C
CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 1.1
November 1999
Samsung Electronics reserves the right to change products or specification without notice.
- 1 - REV. 1.1 Nov. '99

1 Page





V62C5181024LL-70P pdf, ピン配列
K4S643232C
512K x 32Bit x 4 Banks Synchronous DRAM
CMOS SDRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K4S643232C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNGs high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Part NO.
Max Freq.
K4S643232C-TC/L55
183MHz
K4S643232C-TC/L60
166MHz
K4S643232C-TC/L70
143MHz
K4S643232C-TC/L80
125MHz
K4S643232C-TC/L10
100MHz
Interface Package
LVTTL
86
TSOP(II)
Data Input Register
Bank Select
CLK
ADD
LCKE
LRAS LCBR
LWE
LCAS
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK CKE CS RAS CAS WE DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
- 3 - REV. 1.1 Nov. '99


3Pages


V62C5181024LL-70P 電子部品, 半導体
K4S643232C
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Supply voltage
VDD, VDDQ
3.0
3.3
3.6
Input logic high voltage
VIH 2.0 3.0 VDDQ+0.3
Input logic low voltage
VIL -0.3 0 0.8
Output logic high voltage
VOH
2.4
-
-
Output logic low voltage
VOL
-
- 0.4
Input leakage current
ILI -10 - 10
Unit
V
V
V
V
V
uA
Note
4
1
2
IOH = -2mA
IOL = 2mA
3
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS
Latency -55
Operating current
(One bank active)
Burst length = 1
ICC1 tRC tRC(min)
Io = 0 mA
3 140
2-
Precharge standby current
in power-down mode
ICC2P CKE VIL(max), tCC = 15ns
ICC2PS CKE & CLK VIL(max), tCC =
Precharge standby current
in non power-down mode
ICC2N
CKE VIH(min), CS VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
Active standby current in
power-down mode
ICC3P CKE VIL(max), tCC = 15ns
ICC3PS CKE & CLK VIL(max), tCC =
Active standby current in
non power-down mode
(One bank active)
ICC3N
CKE VIH(min), CS VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
Operating current
(Burst mode)
Io = 0 mA
ICC4 Page burst
2 Banks activated
3 220
2-
Refresh current
ICC5 tRC tRC(min)
3 200
2-
Self refresh current
ICC6 CKE 0.2V
Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232C-TC**
5. K4S643232C-TL**
Version
-60 -70 -80
140 130 130
- - 130
2
2
20
10
3
3
30
20
200 180 150
- - 130
200 180 160
- - 160
2
450
Unit Note
-10
115
mA
115
2
mA
mA
mA
mA
mA
mA
130
mA
110
150
mA
150
mA
uA
2
3
4
5
- 6 - REV. 1.1 Nov. '99

6 Page



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