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V62C3802048L-85V の電気的特性と機能

V62C3802048L-85VのメーカーはMosel Vitelic Corpです、この部品の機能は「Ultra Low Power 256K x 8 CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V62C3802048L-85V
部品説明 Ultra Low Power 256K x 8 CMOS SRAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V62C3802048L-85V Datasheet, V62C3802048L-85V PDF,ピン配置, 機能
V62C3802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 40mA at 35ns
- Stand-by: 10 µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single + 2.7 to 3.3V Power Supply
• Equal access and cycle time
• 35/45/55/70/85/100 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
• 48 Ball CSP_BGA
Functional Description
The V62C3802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1, an active HIGH CE2, an acti-
ve LOW OE , and Tri-state I/O’s. This device has an autom-
atic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip En-
able 1 (CE1) with Write Enable (WE ) LOW, and Chip Enab-
le 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance sta-
te when the device is deselected: the outputs are disabled d-
uring a write cycle.
The V62C3802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C3802048L is available in
a 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type
48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP(CSP_BGA see next page)
INPUT BUFFER
A0
A1
A2
A3
A4
A5 Cell Array
A6
A7
A8
A9
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17
I/O8
I/O1
CONTROL
CIRCUIT
OE
WE
CE1
CE2
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REV. 1.2 May 2001 V62C3802048L(L)
1
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 GND
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3

1 Page





V62C3802048L-85V pdf, ピン配列
V62C3802048L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
PT
Tstg
Tbias
Minimum
-0.5
-55
-40
Maximum
4.6
1.0
+150
+85
Unit
V
W
0C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
* Key: X = Don’t Care, L = Low, H = High
OE
X
X
L
H
X
Data
High-Z
High-Z
Data Out
High-Z
Data In
Mode
Standby
Standby
Active, Read
Active, Output Disable
Active, Write
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**)
Parameter
Supply Voltage
Input Voltage
Symbol Min
Typ
Max
VCC 2.7 3.0
Gnd 0.0 0.0
3.3
0.0
VIH 2.2 - VCC + 0.2
VIL -0.5* -
0.6
* VIL min = -2.0V for pulse width less than tRC/2.
** For Industrial Temperature.
Unit
V
V
V
V
REV. 1.2 May 2001 V62C3802048L(L)
3


3Pages


V62C3802048L-85V 電子部品, 半導体
V62C3802048L(L)
Read Cycle (3,9) (Vcc = 2.7 to3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Symbol -55 -70 -85 -100 Unit Note
Read Cycle Time
Min Max Min Max Min Max Min Max
tRC
55 - 70 - 85 - 100 -
ns
Address Access Time
tAA - 55 - 70 - 85 - 100 ns
Chip Enable Access Time
tACE - 55 - 70 - 85 - 100 ns
Output Enable Access Time
tOE - 40 - 40 - 40 - 50 ns
Output Hold from Address Change
tOH
10 - 10 - 10 - 10
-
ns
Chip Enable to Output in Low-Z
tCLZ
10 - 10 - 10 - 10
-
ns 4,5
Chip Disable to Output in High-Z
tCHZ - 25 - 30 - 35 - 40 ns 4,5
Output Enable to Output in Low-Z
tOLZ
5-5- 5 - 5
-
ns 4,5
Output Disable to Output in High-Z
tOHZ
- 20 - 25 - 30 - 35 ns 4,5
Power-Up Time
tPU
0-0- 0 - 0
-
ns
5
Power-Down Time
tPD
- 55 - 70 - 85 - 100 ns
5
Write Cycle (3,11) (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
Symbol -55
-70 -85
-100
Min Max Min Max Min Max Min Max
tWC 55 - 70 - 85 - 100 -
tCW
40 - 60 - 70 - 80
-
tAW
40 - 60 - 70 - 80
-
tAS
0-0- 0 - 0
-
tWP
40 - 50 - 60 - 70
-
tWR
0-0- 0 - 0
-
tDW
25 - 30 - 35 - 40
-
tDH
0-0- 0 - 0
-
tWZ - 25 - 30 - 35 - 40
tOW
5-5- 5 - 5
-
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns 4,5
ns 4,5
REV. 1.2 May 2001 V62C3802048L(L)
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
V62C3802048L-85T

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V62C3802048L-85V

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp


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