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V62C2162048L-55B の電気的特性と機能

V62C2162048L-55BのメーカーはMosel Vitelic Corpです、この部品の機能は「Ultra Low Power 128K x 16 CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V62C2162048L-55B
部品説明 Ultra Low Power 128K x 16 CMOS SRAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V62C2162048L-55B Datasheet, V62C2162048L-55B PDF,ピン配置, 機能
Features
• Low-power consumption
- Active: 65mA ICC at 35ns
- Stand-by: 10 µA (CMOS input/output)
2 µA (CMOS input/output, L version)
• 35/45/55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.2V to 2.7V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOP II / 48-fpBGA
V62C2162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Functional Description
The V62C2162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
TSOPII / 48-fpBGA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Memory Array
1024 X 2048
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont Column Select
A10 A11 A12 A13 A14 A15 A16
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A16 18
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.3 OCT 2001 V62C2162048L(L)
1

1 Page





V62C2162048L-55B pdf, ピン配列
V62C2162048L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
PT
Tstg
Tbias
Minimum
-0.5
-55
-40
Maximum
+4.6
1.0
+150
+85
Unit
V
W
0C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16
H X X X X High-Z
High-Z
L L H L H Data Out High-Z
L L H H L High-Z Data Out
L L H L L Data Out Data Out
L X L L L Data In Data In
L X L L H Data In High-Z
L X L H L High-Z Data In
L H H X X High-Z High-Z
L X X H H High-Z High-Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Mode
Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Output Disable
Output Disable
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**)
Parameter
Supply Voltage
Input Voltage
Symbol
VCC
Gnd
VIH
VIL
Min
2.2
0.0
2.2
-0.5*
Typ
2.5
0.0
-
-
Max
2.7
0.0
VCC + 0.2
0.8
Unit
V
V
V
V
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature
REV. 1.3 OCT 2001 V62C2162048L(L)
3


3Pages


V62C2162048L-55B 電子部品, 半導体
V62C2162048L(L)
Read Cycle (9) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Sym -55 -70 -85 -100 Unit Note
Read Cycle Time
Min Max Min Max Min Max Min Max
tRC 55 - 70 - 85 - 100 -
ns
Address Access Time
tAA - 55 - 70 - 85 - 100 ns
Chip Enable Access Time
tACE - 55 - 70 - 85 - 100 ns
Output Enable Access Time
tOE - 35 - 40 - 40 - 50 ns
Output Hold from Address Change
tOH 10 - 10 - 10 - 10 -
ns
Chip Enable to Output in Low-Z
tLZ 10 - 10 - 10 - 10 -
ns 4,5
Chip Disable to Output in High-Z
tHZ - 25 - 30 - 35 - 40 ns 3,4,5
Output Enable to Output in Low-Z
tOLZ 5 - 5 - 5 - 5
-
ns
Output Disable to Output in High-Z
tOHZ - 25 - 25 - 30 - 35
ns
BLE, BHE Enable to Output in Low-Z
tBLZ 5 - 5 - 5 - 5
-
ns 4,5
BLE, BHE Disable to Output in High-Z tBHZ - 25 - 25 - 30 - 35 ns 3,4,5
BLE, BHE Access Time
tBA - 35 - 40 - 40 - 50 ns
Write Cycle (11) (Vcc = 2.2 to2.7V, Gnd = 0V, T A = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
BLE, BHE Setup to Write End
Symbol -55 -70 -85 -100 Unit Note
Min Max Min Max Min Max Min Max
tWC
55 - 70 - 85 - 100 -
ns
tCW
50 - 60 - 70 - 80
-
ns
tAW
50 - 60 - 70 - 80
-
ns
tAS
0-0-0- 0
-
ns
tWP
45 - 50 - 60 - 70
-
ns
tWR
0-0-0- 0
-
ns
tDW
25 - 30 - 35 - 40
-
ns
tDH
0-0-0- 0
-
ns
tWHZ - 25 - 30 - 35 - 40 ns
tOW
5-5-5- 5
-
ns
tBW
50 - 60 - 70 - 80
-
ns
6
REV. 1.3 OCT 2001 V62C2162048L(L)

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
V62C2162048L-55B

Ultra Low Power 128K x 16 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V62C2162048L-55T

Ultra Low Power 128K x 16 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp


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