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V62C1802048L-85V の電気的特性と機能

V62C1802048L-85VのメーカーはMosel Vitelic Corpです、この部品の機能は「Ultra Low Power 256K x 8 CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V62C1802048L-85V
部品説明 Ultra Low Power 256K x 8 CMOS SRAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V62C1802048L-85V Datasheet, V62C1802048L-85V PDF,ピン配置, 機能
V62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10 µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single + 1.8 to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
Functional Description
The V62C1802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1 , an active HIGH CE2, an act-
ive LOW OE , and Tri-state I/O’s. This device has an auto-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1) with Write Enable (WE) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP
INPUT BUFFER
A0
A1
A2
A3
A4
A5 Cell Array
A6
A7
A8
A9
I/O8
I/O1
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17
CONTROL
CIRCUIT
OE
WE
CE1
CE2
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REV. 1.2 May 2001 V62C1802048L(L)
1
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 GND
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3

1 Page





V62C1802048L-85V pdf, ピン配列
V62C1802048L(L)
DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Parameter
Input Leakage Current
Sym Test Conditions
IILII
Vcc = Max,
Vin = Gnd to Vcc
-70 -85 -100 -150
Unit
Min Max Min Max Min Max Min Max
- 1 - 1 - 1 - 1 µA
Output Leakage
Current
IILOI
CE1 = VIH or CE2 = VIL
Vcc= Max, VOUT = Gnd to Vcc
-
1
-
1
-
1
-
1
µA
Operating Power
Supply Current
ICC CE1 = VIL , CE2 = VIH
VIN = VIHor VIL ,IOUT=0mA
- 3 - 3 - 3 - 3 mA
Average Operating
Current
ICC1 CE1 = VIL , CE2 = VIH
IOUT = 0mA,
Min Cycle, 100% Duty
- 20 - 20 - 15 - 15 mA
ICC2
CE1 = 0.2V ,
CE2 =Vcc - 0.2V
IOUT = 0mA,
Cycle Time=1µs, 100% Duty
- 3 - 3 - 3 - 3 mA
Standby Power Supply ISB CE1 = VIH or CE2 = VIL
Current (TTL Level)
- 0.3 - 0.3 - 0.3 - 0.3 mA
Standby Power Supply ISB1 CE1 > Vcc - 0.2V or
Current (CMOS Level)
CE2 < 0.2V, f = 0
VIN < 0.2V or
VIN > Vcc- 0.2V
- 10 - 10 - 10 - 10 µA
L - 2 - 2 - 2 - 2 µA
Output Low Voltage
VOL IOL = 2 mA
- 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage VOH IOH = -1 mA
1.6 - 1.6 - 1.6 - 1.6 -
V
Capacitance (f = 1MHz, TA = 250C)
Parameter*
Symbol
Input Capacitance
Cin
I/O Capacitance
CI/O
* This parameter is guaranteed by device characterization and is not production tested.
Test Condition
Vin = 0V
Vin = Vout = 0V
Max
7
8
Unit
pF
pF
AC Test Conditions
Input Pulse Level
0.4V to 1.6V
Input Rise and Fall Time
5ns
Input and Output Timing
Reference Level
50% of input level
(VIL+VIH)/2
Output Load Condition
70ns/85 ns
Load 100ns/150 ns
CL = 30pf + 1TTL Load
CL = 100pf + 1TTL Load
CL*
TTL
Figure A.
* Including Scope and Jig Capacitance
REV. 1.2 May 2001 V62C1802048L(L)
3


3Pages


V62C1802048L-85V 電子部品, 半導体
V62C1802048L(L)
Timing Waveform of Write Cycle 1 (10,11) (WE Controlled)
Address
tAW tWC
WE
tWP
tWR
DIN
DOUT
tAS tDW tDH
Data Valid
tWZ tOW
Timing Waveform of Write Cycle 2 (10,11) (CE1 Controlled)
tWC
tAW
tWR
Address
CE1
tAS tCW
WE
tWP
DIN
tWZ tDW tDH
Data Valid
DOUT
Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled)
tWC
tAW
tWR
Address
tAS tCW
CE2
WE
tWP
tWZ tDW tDH
DIN Data Valid
DOUT
REV. 1.2 May 2001 V62C1802048L(L)
6

6 Page



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共有リンク

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部品番号部品説明メーカ
V62C1802048L-85T

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V62C1802048L-85V

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp


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